Patent Assignment
Reel/Frame 051446/0476
Assignment of Assignor's Interest
Recorded: 2019-12-30
Pages: 19
Assignor
ULTRATECH, INC.
Executed: 2019-12-19
Assignee
VEECO INSTRUMENTS INC.
1 TERMINAL DRIVE, PLAINVIEW, NEW YORK, 11803
Covered Properties
(190)
Methods for annealing an integrated device using a radiant energy absorber layer
Patent:
6,300,208 →
Application:
09/505,264 →
Radiation Shield Device and Method
Patent:
6,617,600 →
Application:
09/505,595 →
Laser Thermal Processing Apparatus and Method
Patent:
6,366,308 →
Application:
09/505,605 →
Lead-Free Solder Powder Material, Lead-Free Solder Paste and a Method for Preparing Same
Patent:
6,569,262 →
Application:
09/511,478 →
Solder bump forming method and apparatus
Patent:
6,273,328 →
Application:
09/521,354 →
Copper Pad Structure
In-Situ Ion Implant Activation and Measurement Apparatus
Patent:
6,417,515 →
Application:
09/527,192 →
Method and Structure of Column Interconnect
Patent:
6,495,917 →
Application:
09/527,276 →
Apparatus and Method for Controlling Wafer Environment Between Thermal Clean and Thermal Processing
Patent:
6,488,778 →
Application:
09/527,698 →
Method of and Apparatus for Defining Disk Tracks in Magnetic Recording Media
Patent:
6,671,235 →
Application:
09/536,867 →
At Least One Line Source of Including a Plurality of Laser Diodes to Provide Radiant Energy to Expose a Substrate
Patent:
6,531,681 →
Application:
09/536,869 →
Methods for Annealing a Substrate and Article Produced by Such Methods
Patent:
6,825,101 →
Application:
09/536,927 →
Illumination Fluence Regulation System and Method for Use in Thermal Processing Employed in the Fabrication of Reduced-Dimension Integrated Circuits
Patent:
6,570,656 →
Application:
09/546,114 →
Structure and Method for an Optical Block in Shallow Trench Isolation for Improved Laser Anneal Control
Patent:
6,388,297 →
Application:
09/547,834 →
Method of forming a silicide region in a si substrate and a device having same
Patent:
6,274,488 →
Application:
09/547,836 →
High-Speed Semiconductor Transistor and Selective Absorption Process Forming Same
Patent:
6,380,044 →
Application:
09/548,326 →
Real-Time Evaluation of Stress Fields and Properties in Line Features Formed on Substrates
Patent:
6,600,565 →
Application:
09/560,719 →
High Density Column Grid Array Connections and Method Thereof
Patent:
6,429,388 →
Application:
09/564,110 →
Electrical interconnection package and method thereof
Patent:
6,333,563 →
Application:
09/587,944 →
Thermally induced reflectivity switch for laser thermal processing
Patent:
6,303,476 →
Application:
09/592,184 →
Acousto-optical light tunnel apparatus and method
Patent:
6,347,176 →
Application:
09/595,169 →
Thermally Induced Phase Switch for Laser Thermal Processing
Patent:
6,479,821 →
Application:
09/659,094 →
Method for Annealing Using Partial Absorber Layer Exposed to Radiant Energy and Article Made with Partial Absorber Layer
Patent:
6,635,541 →
Application:
09/659,102 →
Electronic Package Interconnect Structure Comprising Lead-Free Solders
Patent:
6,433,425 →
Application:
09/660,558 →
Process for Making Fine Pitch Connections Between Devices and Structure Made by the Process
Patent:
6,444,560 →
Application:
09/669,531 →
Electrochemical Etch for High Tin Solder Bumps
Patent:
6,468,413 →
Application:
09/697,333 →
Laser Thermal Process for Fabricating Field-Effect Transistors
Patent:
6,365,476 →
Application:
09/698,670 →
Lead-Free Solder Structure and Method for High Fatigue Life
Coherent Gradient Sensing Ellipsometer
Solder Bump Forming Method and Apparatus
System on a Package Fabricated on a Semiconductor or Dielectric Wafer with Wiring on One Face, Vias Extending Through the Wafer, and External Connections on the Opposing Face
Technique for Determining Curvatures of Embedded Line Features on Substrates
Structure to Accommodate Increase in Volume Expansion During Solder Reflow
Lithography System and Method for Device Manufacture
Machine-Independent Alignment System and Method
Patent:
6,898,306 →
Application:
09/855,485 →
Backside Alignment System and Method
Method of Forming a Silicide Region in a Si Substrate and a Device Having Same
Patent:
6,420,264 →
Application:
09/896,160 →
Rework Methods for Lead Bga/Cga
Imaging Stabilization Apparatus and Method for High-Performance Optical Systems
Patent:
6,617,555 →
Application:
09/923,734 →
Method of Forming Thermally Induced Reflectivity Switch for Laser Thermal Processing
Thermally Induced Reflectivity Switch for Laser Thermal Processing
Method for Semiconductor Gate Doping
Method and Apparatus for Mechanically Masking a Workpiece
Patent:
6,680,774 →
Application:
09/973,790 →
High Density Interconnects
Method for Forming Solder Connections on a Circuitized Substrate
High Density Raised Stud Microjoining System and Methods of Fabricating the Same
High Density Area Array Solder Microjoining Interconnect Structure and Fabrication Method
Method for Laser Thermal Processing Using Thermally Induced Reflectivity Switch
Patent:
6,635,588 →
Application:
10/078,842 →
Method and Structure for Joining Two Substrates with a Low Melt Solder Joint
Patent:
6,583,517 →
Application:
10/119,491 →
Selective Absorption Process for Forming an Activated Doped Region in a Semiconductor
Patent:
6,645,838 →
Application:
10/122,955 →
Smt Passive Device Noflow Underfill Methodology and Structure
Method of Forming a Lead-Free Tin-Silver-Copper Based Solder Alloy on an Electronic Substrate.
Patent:
6,596,621 →
Application:
10/151,075 →
Determining Large Deformations and Stresses of Layered and Graded Structures to Include Effects of Body Forces
Ball Grid Array Module and Method of Manufacturing Same
Electronic Package Interconnect Structure Comprising Lead-Free Solders
Dual-Sided Substrate Measurement Apparatus and Methods
Patent:
7,528,937 →
Application:
10/213,868 →
Process for Making Fine Pitch Connections Between Devices and Structure Made by the Process
Negative Volume Expansion Lead-Free Electrical Connection
Patent:
6,649,833 →
Application:
10/215,451 →
Dual-Solder Flip-Chip Solder Bump
Lead-Free Alloys for Column/Ball Grid Arrays, Organic Interposers and Passive Component Assembly
Selective C4 Connection in Ic Packaging
Patent:
6,650,016 →
Application:
10/262,753 →
Multi-Layered Interconnect Structure Using Liquid Crystalline Polymer Dielectric
Laser Scanning Apparatus and Methods for Thermal Processing
Large-Field Unit-Magnification Projection System
Variable Numerical Aperture Large-Field Unit-Magnification Projection System
Selective Filling of Electrically Conductive Vias for Three Dimensional Device Structures
Method and System for Laser Thermal Processing of Semiconductor Devices
Patent:
6,844,250 →
Application:
10/390,504 →
Deep Ultraviolet Unit-Magnification Projection Optical System and Projection Exposure Apparatus
Method of Fabricating Integrated Electronic Chip with an Interconnect Device
Improvements in Grounding and Thermal Dissipation for Integrated Circuit Packages
Systems for Measuring Stresses in Line Features Formed on Substrates
Laser Thermal Processing with Laser Diode Radiation
Laser Thermal Annealing of Lightly Doped Silicon Substrates
High Density Area Array Solder Microjoining Interconnect Structure and Fabrication Method
Electronic Package with Improved Current Carrying Capability and Method of Forming the Same
Laser Thermal Annealing of Lightly Doped Silicon Substrates
Full-Field Optical Measurements of Surface Properties of Panels, Substrates and Wafers
Laser Scanning Apparatus and Methods for Thermal Processing
High Surface Area Aluminum Bond Pad for Through-Wafer Connections to an Electronic Package
High Na Large-Field Unit-Magnification Projection Optical System
Patent:
7,116,496 →
Application:
10/976,971 →
Apochromatic Unit-Magnification Projection Optical System
Heated Chuck for Laser Thermal Processing
Laser Thermal Processing Chuck with a Thermal Compensating Heater Module
Deep Ultraviolet Unit-Magnification Projection Optical System and Projection Exposure Apparatus
Heat Shield for Thermal Processing
Electronic Package with Optimized Lamination Process
Vapor Deposition Systems and Methods
Method for Forming C4 Connections on Integrated Circuit Chips and the Resulting Devices
Apparatus and Methods for Improving the Intensity Profile of a Beam Image Used to Process a Substrate
Patent:
7,514,305 →
Application:
11/476,275 →
Laser Thermal Annealing of Lightly Doped Silicon Substrates
Laser Thermal Annealing of Lightly Doped Silicon Substrates
Integrated Chip Carrier with Compliant Interconnect
Method of Fabricating a Bga Package Having Decreased Adhesion
Method of Reducing Detrimental Sti-Induced Stress in Mosfet Channels
Techniques for Forming Interconnects
Patent:
7,348,270 →
Application:
11/625,449 →
Method of Removing Metallic, Inorganic and Organic Contaminants from Chip Passivation Layer Surfaces
Determination of Lithography Misalignment Based on Curvature and Stress Mapping Data of Substrates
Silicon Germanium Heterojunction Bipolar Transistor Structure and Method
Methodology for Recovery of Hot Carrier Induced Degradation in Bipolar Devices
Methods of Forming a Denuded Zone in a Semiconductor Wafer Using Rapid Laser Annealing
Methods and Apparatus for Temperature Measurement and Control on a Remote Substrate Surface
Patent:
7,744,274 →
Application:
11/820,558 →
Semiconductor Device and Method of Manufacture
Method of Forming Cmos with Si:C Source/Drain by Laser Melting and Recrystallization
Through Silicon via and Method of Fabricating Same
Vertical Through-Silicon via for a Semiconductor Structure
Dual-Sided Substrate Measurement Apparatus and Methods
Patent:
7,902,040 →
Application:
12/286,762 →
Apparatus and Methods for Improving the Intensity Profile of a Beam Image Used to Process a Substrate
Patent:
8,153,930 →
Application:
12/381,061 →
Activating Dopants Using Multiple Consecutive Millisecond-Range Anneals
Laser Spike Annealing for Gan Leds
Optical Alignment Methods for Forming Leds Having a Rough Surface
Reaction Chamber with Removable Liner
System and Method for Thin Film Deposition
Method for Forming Retrograded Well for Mosfet
Through Silicon via Lithographic Alignment and Registration
Silicon Germanium Heterojunction Bipolar Transistor Structure and Method
Wafer Level Integrated Interconnect Decal and Manufacturing Method Thereof
Electrical Interconnect Structure
Electrical Interconnect Forming Method
Electrical Interconnect Forming Method
Sub-Field Enhanced Global Alignment
Through Substrate via Including Variable Sidewall Profile
Integrated Chip Carrier with Compliant Interconnects
Phase-Shift Mask with Assist Phase Regions
Laser Annealing for 3-D Chip Integration
Ultrafast Laser Annealing with Reduced Pattern Density Effects in Integrated Circuit Fabrication
Patent:
8,309,474 →
Application:
13/134,408 →
Activating Gan Leds by Laser Spike Annealing and Flash Annealing
Systems and Methods for Forming a Time-Averaged Line Image
Apparatuses and Methods for Irradiating a Substrate to Avoid Substrate Edge Damage
Fast Thermal Annealing of Gan Leds
Ald Systems and Methods
Vapor Deposition Systems and Methods
Apparatus and Method for Improving the Intensity Profile of a Beam Image Used to Process a Substrate
Patent:
8,742,286 →
Application:
13/354,300 →
Two-Beam Laser Annealing with Improved Temperature Performance
Through Silicon via for Use in Integrated Circuit Chips
Substrate-Alignment Using Detector of Substrate Material
Patent:
44,116 →
Application:
13/366,199 →
Laser Annealing Scanning Methods with Reduced Annealing Non-Uniformities
Patent:
8,501,638 →
Application:
13/459,031 →
LED-based photolithographic illuminator with high collection efficiency
Non-melt thin-wafer laser thermal annealing methods
Ultrafast laser annealing with reduced pattern density effects in integrated circuit fabrication
Movable microchamber system with gas curtain
Dual-Loop Control for Laser Annealing of Semiconductor Wafers
Patent:
8,691,598 →
Application:
13/706,397 →
Wynn-Dyson imaging system with reduced thermal distortion
Underfill Flow Guide Structures and Method of Using Same
Silicon Germanium Heterojunction Bipolar Transistor Structure and Method
Unit magnification large-format catadioptric lens for microlithography
Laser Annealing Systems and Methods with Ultra-Short Dwell Times
Substrate Processing with Reduced Warpage and/or Controlled Strain
Betavoltaic power sources for transportation applications
Methods of laser processing photoresist in a gaseous environment
Two-Beam Laser Annealing with Improved Temperature Performance
Through Silicon via and Method of Fabricating Same
Dual-Loop Control for Laser Annealing of Semiconductor Wafers
Apparatus and methods for improving the intensity profile of a beam image used to process a substrate
Wynne-Dyson projection lens with reduced susceptibility to UV damage
Systems and methods for reducing beam instability in laser annealing
Wynne-Dyson optical system with variable magnification
Laser Annealing Systems and Methods with Ultra-Short Dwell Times
Laser Spike Annealing Using Fiber Lasers
Method for High-Velocity and Atmospheric-Pressure Atomic Layer Deposition with Substrate and Coating Head Separation Distance in the Millimeter Range
Method of laser annealing a semiconductor wafer with localized control of ambient oxygen
High-efficiency line-forming optical systems and methods
Formation of Heteroepitaxial Layers with Rapid Thermal Processing to Remove Lattice Dislocations
Method and Apparatus for Forming Device Quality Gallium Nitride Layers on Silicon Substrates
High-Efficiency Line-Forming Optical Systems and Methods for Defect Annealing and Dopant Activation
Laser Annealing Systems and Methods with Ultra-Short Dwell Times
Atomic Layer Deposition Head
Plasma Enhanced Ald System
Systems and methods for reducing pulsed laser beam profile non-uniformities for laser annealing
Microchamber laser processing systems and methods using localized process-gas atmosphere
Application:
15/145,833 →
Publication:
US 2016/0354865
Polarization-Based Coherent Gradient Sensing Systems and Methods
Masking methods for ALD processes for electrode-based devices
High-efficiency line-forming optical systems and methods using a serrated spatial filter
Silicon Germanium Heterojunction Bipolar Transistor Structure and Method
Plasma Atomic Layer Deposition System and Method
Application:
15/277,096 →
Publication:
US 2017/0016114
Methods of forming an ALD-inhibiting layer using a self-assembled monolayer
Systems and methods of characterizing process-induced wafer shape for process control using CGS interferometry
High-efficiency line-forming optical systems and methods for defect annealing and dopant activation
Method and Apparatus for Forming Device Quality Gallium Nitride Layers on Silicon Substrates
Formation of Heteroepitaxial Layers with Rapid Thermal Processing to Remove Lattice Dislocations
Formation of Heteroepitaxial Layers with Rapid Thermal Processing to Remove Lattice Dislocations
Wafer Chuck Apparatus With Micro-Channel Regions
Scanning Methods for Focus Control for Lithographic Processing of Reconstituted Wafers
Wafer Chuck Apparatus With Contractible Sealing Devices For Securing Warped Wafers
Application:
15/834,718 →
Publication:
US 2018/0166314
Chuck Systems and Methods Having Enhanced Electrical Isolation For Substrate-Biased ALD
Laser-Assisted Atomic Layer Deposition of 2D Metal Chalcogenide Films
Method and Apparatus for Forming Device Quality Gallium Nitride Layers on Silicon Substrates
Laser-Based Systems and Methods for Melt-Processing of Metal Layers in Semiconductor Manufacturing
Laser Annealing Systems and Methods With Ultra-Short Dwell Times
Plasma Enhanced ALD System
Application:
16/429,850 →
Publication:
US 2019/0284689
High-Efficiency Line-Forming Optical Systems and Methods Using A Serrated Spatial Filter
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 13, 2012
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ULTRATECH, INC.
Reel/Frame 028959/0001 →
Assignment of Assignor's Interest
Jan 10, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ULTRATECH, INC.
Reel/Frame 031941/0821 →
Assignment of Assignor's Interest
Jun 17, 2014
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ULTRATECH, INC.
Reel/Frame 033122/0154 →
Assignment of Assignor's Interest
May 7, 2020
From: VEECO INSTRUMENTS INC.
To: KLA CORPORATION
Reel/Frame 052594/0086 →