Integrated chip carrier with compliant interconnects
View Patent ↗A silicon chip includes a silicon substrate, a plurality of pads, and a plurality of through vias to connect back-end-of-line wiring to the plurality of pads. The silicon substrate includes a layer of active devices and the back-end-of-line wiring connected to the active devices.
1. A silicon chip package comprising:
a carrier comprising a first coefficient of thermal expansion;
an organic substrate connected to a bottom surface of the carrier, said organic substrate comprising:
a second coefficient of thermal expansion providing a mismatch with the first coefficient of thermal expansion;
a layer of active devices comprising a third coefficient of thermal expansion approximately matching the first coefficient of thermal expansion; and
back-end-of-line wiring connected to the active devices;
a plurality of pads exposed at a bottom surface of the carrier; and
a plurality of through vias to connect the back-end-of-line wiring to the plurality of the pads, each of the plurality of through vias comprising:
a collar exposed at a top surface of the carrier;
a pad exposed at a bottom surface of the carrier; and
a through via post disposed between the collar and the pad.
2. The silicon chip of claim 1 in which the plurality of through vias are completely filled with a conductive metal.
3. The silicon chip of claim 2 wherein the vias are fabricated from copper.
4. The silicon chip of claim 1 in which the through via post is freely floating, extending through a volume of empty space.
5. The silicon chip of claim 1 in which the plurality of through vias are filled with a low modulus material softly supporting the through via post.
6. The silicon chip of claim 1 in which the through via post is placed at an angle which is not perpendicular to the organic substrate, providing compliance in a vertical direction while providing compliance in longitudinal directions.
7. The silicon chip of claim 6 wherein the post is fabricated at angle between 30 and 45 degrees.
8. The silicon chip of claim 6 wherein the post is fabricated with a curved section.
9. The silicon chip of claim 8 wherein the post is S-shaped.
10. The silicon chip of claim 6 wherein the post is L-shaped.
11. The silicon chip of claim 1 wherein the carrier is fabricated from silicon.
12. The silicon chip of claim 1 wherein the organic substrate is connected to the bottom surface of the carrier by solder bumps.
13. A silicon chip comprising:
a top surface; and
a bottom surface;
a silicon substrate comprising a layer of active devices at the top surface of the silicon chip; and
back-end-of-line wiring connected below the layer of active devices;
a plurality of pads disposed along the bottom surface of the silicon chip; and
a plurality of through vias that connect the back-end-of-line wiring to the plurality of the pads, each of the plurality of through vias comprising:
a collar exposed at a top surface of the substrate; and
a through via post disposed between the collar and the pad, said through via post placed at an angle which is not perpendicular to the substrate, providing compliance in a vertical direction while providing compliance in longitudinal directions.
14. The silicon chip of claim 13 wherein the back-end-of-line wiring is connected below the layer of the active devices using silicon on insulator technology.