IP Library Assignment 033519/0066
Patent Assignment
Reel/Frame 033519/0066

Assignment of Assignor's Interest

Recorded: 2014-08-12 Pages: 8
Assignor
Assignee
ULTRATECH, INC.
3050 ZANKER ROAD, SAN JOSE, CALIFORNIA, 95134
Covered Properties (27)
Method for Assembling a Chip Carrier to a Semiconductor Device
Patent: 6,220,499 →
Application: 09/163,150 →
Multi-Voltageplane, Multi-Signal Plane Circuit Card with Dotoimageable Dielectric
Patent: 6,201,194 →
Application: 09/203,978 →
High Density Interconnects
Patent: 6,764,313 →
Application: 10/038,483 →
Publication: US 2004/0048497
Method for Forming Solder Connections on a Circuitized Substrate
Patent: 6,708,871 →
Application: 10/041,392 →
Publication: US 2003/0127500
Electronic Package with High Density Interconnect Layer
Patent: 6,829,823 →
Application: 10/067,551 →
Publication: US 2002/0085364
Smt Passive Device Noflow Underfill Methodology and Structure
Patent: 6,739,497 →
Application: 10/145,467 →
Publication: US 2003/0209590
Process for Making Fine Pitch Connections Between Devices and Structure Made by the Process
Patent: 6,737,297 →
Application: 10/213,872 →
Publication: US 2003/0015788
Selective C4 Connection in Ic Packaging
Patent: 6,650,016 →
Application: 10/262,753 →
Method of Fabricating Integrated Electronic Chip with an Interconnect Device
Patent: 6,864,165 →
Application: 10/605,204 →
Publication: US 2005/0056942
Semiconductor Module with Improved Interposer Structure and Method for Forming the Same
Patent: 7,245,022 →
Application: 10/721,984 →
Publication: US 2005/0110160
Electronic Package with Improved Current Carrying Capability and Method of Forming the Same
Patent: 7,332,805 →
Application: 10/752,176 →
Publication: US 2005/0146016
Methodology for Recovery of Hot Carrier Induced Degradation in Bipolar Devices
Patent: 7,238,565 →
Application: 10/904,985 →
Publication: US 2006/0118912
Electronic Package with Optimized Lamination Process
Patent: 7,329,816 →
Application: 11/148,890 →
Publication: US 2005/0224961
Smt Passive Device Noflow Underfill Methodology and Structure
Patent: 7,408,264 →
Application: 11/497,685 →
Publication: US 2006/0290008
Integrated Chip Carrier with Compliant Interconnect
Patent: 7,473,577 →
Application: 11/502,969 →
Publication: US 2008/0036061
Electronic Package with Improved Current Carrying Capability and Method of Forming the Same
Patent: 7,407,883 →
Application: 11/529,027 →
Publication: US 2007/0045816
Method of Reducing Detrimental Sti-Induced Stress in Mosfet Channels
Patent: 7,618,857 →
Application: 11/623,935 →
Publication: US 2008/0171413
Modification of Solder Alloy Compositions to Suppress Interfacial Void Formation in Solder Joints
Patent: 8,157,158 →
Application: 11/669,076 →
Publication: US 2008/0182124
Semiconductor Device and Method of Manufacture
Patent: 7,615,435 →
Application: 11/830,867 →
Publication: US 2009/0032840
Thermo-Compression Bonded Electrical Interconnect Structure and Method
Patent: 8,043,893 →
Application: 11/855,236 →
Publication: US 2009/0075469
Method of Forming Cmos with Si:C Source/Drain by Laser Melting and Recrystallization
Patent: 7,598,147 →
Application: 11/860,127 →
Publication: US 2009/0081836
Optimization of Metallurgical Properties of a Solder Joint
Patent: 8,197,612 →
Application: 12/111,524 →
Publication: US 2009/0266447
Flexible Printed Circuits Capable of Transmitting Electrical and Optical Signals
Patent: 7,492,985 →
Application: 12/166,442 →
Publication: US 2008/0267556
Elliptic C4 with Optimal Orientation for Enhanced Reliability in Electronic Packages
Patent: 8,047,421 →
Application: 12/869,340 →
Publication: US 2011/0049711
Thermo-Compression Bonded Electrical Interconnect Structure
Patent: 8,164,192 →
Application: 12/984,707 →
Publication: US 2011/0095431
Integrated Chip Carrier with Compliant Interconnects
Patent: 8,344,516 →
Application: 12/986,460 →
Publication: US 2011/0101540
Laser Annealing for 3-D Chip Integration
Patent: 8,138,085 →
Application: 13/093,798 →
Publication: US 2011/0201199
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Dec 30, 2019
From: ULTRATECH, INC.
To: VEECO INSTRUMENTS INC.
Reel/Frame 051383/0735 →
Assignment of Assignor's Interest Dec 30, 2019
From: ULTRATECH, INC.
To: VEECO INSTRUMENTS INC.
Reel/Frame 051446/0476 →
Patent Security Agreement Dec 16, 2021
From: VEECO INSTRUMENTS INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 058533/0321 →
Security Interest Jun 16, 2025
From: VEECO INSTRUMENTS INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 071649/0225 →