Electronic package with optimized lamination process
View Patent ↗An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T 1MIN and a maximum temperature T 1MAX . T 1MAX constrains the ductility of the first dielectric layer to be at least D 1 following the laminating. T 1MAX depends on D 1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T 2MIN and a maximum temperature T 2MAX . T 2MAX constrains the ductility of the second dielectric layer to be at least D 2 following the laminating. T 2MAX depends on D 2 and on a second dielectric material comprised by the second dielectric layer.
1. A multi-layered interconnect structure, comprising:
a thermally conductive layer including first and second opposing surfaces;
a first dielectric layer laminated to said first opposing surface of said thermally conductive layer such that the first dielectric layer includes a first dielectric material and has a ductility of at least about D 1 ;
a second dielectric layer laminated to said second opposing surface of said thermally conductive layer such that the second dielectric layer includes a second dielectric material and has a ductility of at least about D 2 ;
first and second pluralities of electrically conductive members positioned on said first and second dielectric layers, respectively;
a first electrically conductive layer within said first dielectric layer;
a second electrically conductive layer within said first dielectric layer and positioned between said first electrically conductive layer and said thermally conductive layer, wherein said second electrically conductive layer comprises a first plurality of shielded signal conductors;
a plated through hole through the multi-layered interconnect structure electrically connected to at least one member of said first plurality of electrically conductive members, to at least one of said first plurality of shielded signal conductors, and to at least one member of said second plurality of electrically conductive members; and
a third dielectric layer positioned on said first dielectric layer and on portions of said first plurality of electrically conductive members, said third dielectric layer substantially overlying said plated through hole, and wherein said third dielectric layer includes a first high density interconnect layer for providing an electrical path from a first electronic device to the first plurality of shielded signal conductors.
2. The multi-layered interconnect structure of claim 1 , wherein D 1 =8%, and wherein D 2 =8%.
3. The multi-layered interconnect structure of claim 1 , wherein D 1 =100%, and wherein D 2 =100%.
4. The multi-layered interconnect structure of claim 1 , wherein the first dielectric material comprises silica filled polytetrafluoroethylene, and wherein the second dielectric material comprises silica filled polytetrafluoroethylene.
5. The multi-layered interconnect structure of claim 1 , wherein said third dielectric layer includes a resin comprising an allylated polyphenylene ether.
6. The multi-layered interconnect structure of claim 1 , further comprising:
a third electrically conductive layer within said second dielectric layer;
a fourth electrically conductive layer within said second dielectric layer and positioned between said third electrically conductive layer and said thermally conductive layer, wherein said fourth electrically conductive layer comprises a second plurality of shielded signal conductors; and
a fourth dielectric layer positioned on said second dielectric layer and on portions of said second plurality of electrically conductive members, said fourth dielectric layer substantially overlying said plated through hole, wherein said fourth dielectric layer includes a second high density interconnect layer for providing an electrical path from a second electronic device to the second plurality of shielded signal conductors.
7. The multi-layered interconnect structure of claim 6 , wherein said fourth dielectric layer includes a resin comprising an allylated polyphenylene ether.
8. The multi-layered interconnect structure of claim 6 , further comprising:
a first plated blind via in the third dielectric layer, wherein the first plated blind via is conductively coupled to the at least one member of said first plurality of electrically conductive members;
a second plated blind via in the fourth dielectric layer, wherein the second plated blind via is conductively coupled to the at least one member of said second plurality of electrically conductive members,
a first solder connection conductively coupled to the first plated blind via;
a second solder connection conductively coupled to the second plated blind via; a first electronic device conductively coupled by the first solder connection to the first plated blind via; and
a second electronic device conductively coupled by the second solder connection to the second plated blind via.
9. The multi-layered interconnect structure of claim 8 , wherein the first electronic device is a semiconductor chip, and wherein second electronic device is a circuitized substrate.