Integrated chip carrier with compliant interconnect
View Patent ↗An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top side connected to the bottom side of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a plurality of through vias from the bottom side of the carrier to the top side of the carrier layer. Each through via comprising a collar exposed at the top surface of the carrier, a pad exposed at the bottom surface of the carrier, and a post disposed between the collar and the pad. The post extends thorough a volume of space.
1. A method of fabricating a compliant through via in a silicon carrier, the method comprising:
patterning the silicon carrier;
etching an annulus into the silicon carrier using deep reactive ion etching processes;
insulating the annulus using a thermally grown oxide;
filling the annulus with a compliant material;
patterning the silicon;
performing a reactive ion etch to remove the oxide and a deep reactive ion etching to remove a silicon center post;
re-patterning the silicon to form a through hole in the silicon;
copper plating the silicon to form a via collar;
postgrinding a backside of the silicon carrier to expose a copper post;
patterning the backside of the carrier and plating the carrier to form a copper pad and ball limiting metallurgy; and
fabricating solder bumps onto the ball limiting metallurgy using a transfer method.
2. The method of claim 1 , wherein the annulus is filled with a low modulus material.
3. The method of claim 1 , wherein the annulus is filled with a photo resist material.
4. A method of fabricating though vias in a carrier, the method comprising:
patterning a silicon substrate;
etching an annular via in the substrate using deep reactive ion etching;
growing a thermal oxide on the silicon substrate;
filling the annular via with poly silicon to produce a polysilicon annular via;
planarizing and oxidizing the silicon substrate;
patterning a top surface of the silicon substrate with photoresist;
etching both oxide and silicon of the silicon substrate to a depth beyond the polysilicon annular via;
patterning the top surface with copper to form a via collar and post;
thinning a backside of the silicon substrate to expose a copper via post;
patterning the backside of the silicon substrate;
plating the silicon substrate to form a copper pad and ball limiting metallurgy;
patterning the backside of the silicon substrate to expose silicon surrounding the copper via post; and
etching the silicon surrounding the copper via post with xenon difluoride.