Laser annealing scanning methods with reduced annealing non-uniformities
View Patent ↗Laser annealing scanning methods that result in reduced annealing non-uniformities in semiconductor device structures under fabrication are disclosed. The methods include defining a length of an annealing laser beam such that the tails of the laser beam resided only within scribe lines that separate the semiconductor device structures. The annealing laser beam tails from adjacent scan path segments can overlap or not overlap within the scribe lines. The cross-scan length of the annealing laser beam can be selected to simultaneously scan more than one semiconductor device structure, as long as annealing laser beam is configured such that the tails do not fall within a semiconductor device structure.
1. A method of annealing semiconductor device structures supported by a semiconductor wafer, comprising:
providing the semiconductor wafer having a wafer surface, with the semiconductor device structures having a cross-scan width WD and spaced apart by scribe lines having a cross-scan width WS:
defining a length L of an annealing laser beam that satisfies the relationship n·WD+(n−1)·WS<L<n·WD+(n+1)·WS for integer n, the annealing laser beam having a central section of substantially uniform intensity and opposite tails of substantially reduced intensity as compared to the central section; and
scanning the annealing laser beam over the semiconductor device structures over a scan path having adjacent scan path segments such that the center section simultaneously passes over at least n semiconductor devices while the tails of the annealing laser beam associated with the adjacent scan path segments reside only within the scribe lines.
2. The method according to claim 1 , wherein the length L is selected such that the tails of the annealing laser beam associated with the adjacent scan path segments overlap within the scribe lines.
3. The method according to claim 1 , wherein the length L is selected such that the tails of the annealing laser beam associated with the adjacent scan path segments reside within the scribe lines but do not overlap within the scribe lines.
4. The method according to claim 1 , wherein the semiconductor device structures comprise dies and the scribe lines reside between the dies.
5. The method according to claim 1 , wherein the semiconductor device structures comprise dies that in turn include integrated circuit (IC) chips, and wherein the scribe lines reside between the IC chips and between the dies.
6. A method of laser annealing semiconductor device structures supported by a semiconductor wafer, comprising:
providing the semiconductor wafer such that the semiconductor device structures are spaced apart by scribe lines;
defining an annealing laser beam having a central section of substantially uniform intensity and opposite tails of substantially reduced intensity as compared to the central section;
scanning a laser beam over the semiconductor wafer and the semiconductor device structures such that the central section simultaneously covers the entirety of one or more semiconductor device structures while the tails reside entirely within the scribe lines.
7. The method according to claim 6 , further comprising performing the scanning over a scan path having adjacent scan path segments, and wherein the tails of the annealing laser beam associated with the adjacent scan path segments overlap within the scribe lines.
8. The method according to claim 6 , further comprising performing the scanning over a scan path having adjacent scan path segments, and wherein the tails of the annealing laser beam associated with the adjacent scan path segments do not overlap within the scribe lines.
9. The method according to claim 6 , wherein the scribe lines have a cross-scan width in the range from 50 microns to 75 microns.
10. The method according to claim 6 , wherein the semiconductor device structures have a cross-scan width WD, the scribe lines have a cross-scan width WS, and wherein the annealing laser beam has a length L that satisfies the relationship for integer n:
n·WD +( n− 1)· WS<L<n·WD +( n+ 1)· WS.