Method of removing metallic, inorganic and organic contaminants from chip passivation layer surfaces
View Patent ↗A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO 4 ) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O 2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.
1. A method to process a circuit assembly, comprising:
placing a wafer with the circuit assembly in a process chamber; and
exposing the wafer to a plasma state that is generated with a mixture of Argon (Ar) and Oxygen (O 2 ) in a range of about 80% Ar and about 20% O 2 to about 95% Ar and about 5% O 2 by volume, for a period of time sufficient to remove substantially all of a graphitic/fluorinated polymer layer and at least some of a tin residue, where exposing occurs at a gas pressure in a range of about 10 mTorr to about 500 mTorr, at a plasma power in a range of about 100 W to about 1000 W, and where the period of time is in a range of about 1 minute to about 30 minutes, where the wafer comprises a semiconductor wafer upon which are mounted solder balls; and
repeating the exposing the wafer to the plasma state that is generated with the mixture of Ar and O 2 until a sufficient amount of the tin residue is removed.
2. The method to process a circuit assembly as in claim 1 , where the solder balls comprise lead.
3. The method to process a circuit assembly as in claim 1 , where the solder balls comprise mostly tin but no lead.
4. The method to process a circuit assembly as in claim 1 , where the circuit assembly comprises a passivation layer, and where plasma removes substantially all of the graphitic/fluorinated polymer layer and at least some of the tin residue from the passivation layer.
5. The method to process a circuit assembly as in claim 1 , where about 30% to about 99% of the tin residue is removed by the plasma.
6. A method to process a circuit assembly as in claim 1 , where exposing occurs at a pressure in a range of about 200 mTorr to about 300 mTorr.
7. A method to process a circuit assembly as in claim 1 , where exposing occurs at a plasma power in a range of about 500 W to about 700 W.
8. A method to process a circuit assembly as in claim 1 , where the period of time is in a range of about 5 minutes to about 10 minutes.
9. A method for removing contaminants from a passivation layer, comprising:
forming a gas mixture comprised of about 80% Ar and about 20% O 2 to about 95% Ar and about 5% O 2 by volume;
exposing the passivation layer disposed on a wafer arrangement to the gas mixture in a plasma chamber where a plasma state is created, the wafer arrangement including a passivation layer and solder balls, where the exposing occurs at a gas pressure in a range of about 10 mTorr to about 500 mTorr, at a plasma power in a range of about 100 W to about 1000 W, for a duration in a range of about 1 minute to about 30 minutes, where the wafer arrangement comprises a semiconductor wafer upon which the passivation layer is disposed and solder balls are mounted on the passivation layer, where the plasma removes substantially all of a graphitic/fluorinated polymer layer and at least some of a tin residue from the passivation layer; and
repeating the exposing the passivation layer to the plasma state that is generated with the mixture of Ar and O 2 until a sufficient amount of the tin residue is removed.
10. The method as in claim 9 , where about 30% to about 99% of the tin residue is removed by the plasma.
11. The method as in claim 9 , where exposing occurs at a gas pressure in a range of about 200 mTorr to about 300 mTorr and at a plasma power in a range of about 500 W to about 700 W.
12. The method as in claim 9 , where exposing occurs for a duration in a range of about 5 minutes to about 15 minutes.
13. The method to process a circuit assembly as in claim 1 , further comprising dicing up the wafer; and assembling one or more electronic packages from the diced up wafer.
14. The method as in claim 9 , further comprising dicing up the wafer arrangement; and assembling one or more electronic packages from the diced up wafer arrangement.
15. The method as in claim 9 , where the exposing occurs at a pressure in a range of about 200 mTorr to about 300 mTorr and at a plasma power in a range of about 500 W to about 700 W and the period of time is in a range of about 5 minutes to about 10 minutes.
16. The method as in claim 1 , wherein the tin residue comprises an organotin residue.
17. The method as in claim 1 , wherein the tin residue comprises an inorganic tin residue.
18. The method as in claim 9 , wherein the tin residue comprises an organotin residue.
19. The method as in claim 9 , wherein the tin residue comprises an inorganic tin residue.