Through silicon via and method of fabricating same
View Patent ↗A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.
1. A method, comprising:
(a) forming a trench in a silicon substrate, said trench open to a top surface of said substrate;
(b) forming a silicon dioxide layer on sidewalls of said trench, said silicon dioxide layer not filling said trench;
(c) filling remaining space in said trench with polysilicon;
after (c), (d) fabricating at least a portion of a CMOS device in said substrate;
(e) completely removing said polysilicon from said trench, said silicon dioxide layer remaining on said sidewalls of said trench;
(f) re-filling said trench with an electrically conductive core, said electrically conductive core extending above a top surface of said substrate; and
after (f), (g) forming a stack of two or more damascene wiring levels from a first wiring level to a last wiring level over said top surface of said substrate, a wire of said first wiring level contacting a top surface of said conductive core.
2. The method of claim 1 , further including:
(h) thinning said substrate from a bottom surface to form a thinned substrate, after said thinning a bottom surface of said core coplanar with a bottom surface of said thinned substrate.
3. The method of claim 2 , further including:
forming an interconnect structure to said bottom surface of said core.
4. The method of claim 3 , wherein said forming said interconnect structure includes:
forming a dielectric layer on said bottom surface of said thinned substrate;
forming an opening in said dielectric layer, said core exposed in a bottom of said opening;
forming a metal pad on said dielectric layer; a perimeter of said pad overlapping a perimeter of said opening, said pad contacting said bottom surface of said core; and
forming a solder bump on said metal pad.
5. The method of claim 1 , wherein said silicon dioxide layer is formed by thermal oxidation of said substrate exposed on said sidewalls of said trench.
6. The method of claim 1 , wherein said silicon dioxide layer is at least about 0.5 micron thick.
7. The method of claim 6 , wherein said silicon dioxide layer has a thickness variation of less than about 10% between thinnest and thickest regions of said silicon dioxide layer on said sidewalls of said trench.
8. The method of claim 1 , wherein (a) includes:
forming an oxidation barrier on said top surface of said substrate;
forming an opening in said oxidation barrier, a region of said top surface of said substrate exposed in said opening; and
plasma etching said substrate exposed in said opening.
9. The method of claim 1 , wherein (a) includes:
forming an oxidation barrier layer on a top surface of said substrate;
forming a patterned photoresist layer on a top surface of said barrier layer;
etching said barrier layer to expose said top surface of said substrate where said barrier layer is not protected by said patterned photoresist layer;
after etching said barrier layer, etching said substrate to form said trench; and
after etching said trench and before (b), removing said photoresist layer.
10. The method of claim 1 , further including:
between (b) and (c), forming a pad dielectric layer on said top surface of said substrate and exposed surfaces of said silicon dioxide layer.
11. The method of claim 10 , further including:
between (c) and (d), removing an upper region of said polysilicon in said trench and forming a dielectric cap on remaining polysilicon in said trench.
12. The method of claim 1 , wherein said CMOS device is a field effect transistor and (d) includes:
after forming said field effect transistor, forming a passivation layer over said top surface of said substrate;
forming metal contacts to a source, a drain and a gate electrode of said field effect transistor through said passivation layer; and
forming an opening in said passivation layer over said trench.
13. The method of claim 12 , wherein after performing (f) an upper region of said core fills said opening in said passivation layer.
14. The method of claim 1 , wherein said trench has straight sidewalls perpendicular to said top surface of said wafer and a substantially uniform width.
15. The method of claim 1 , wherein said trench has straight sidewalls tapering toward each other such that a first width of said trench at said top surface of said trench is greater than a second width of said trench at a bottom of said trench.
16. The method of claim 1 , wherein said trench has straight sidewalls tapering away from each other, such that a first width of said trench at said top surface of said trench is less than a second width of said trench at a bottom of said trench.