Patent Assignment
Reel/Frame 028959/0001
Assignment of Assignor's Interest
Recorded: 2012-09-13
Pages: 27
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2012-07-18
Assignee
ULTRATECH, INC.
3050 ZANKER ROAD, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(50)
Method for Forming Reflowed Solder Ball with Low Melting Point Metal Cap
Patent:
6,344,234 →
Application:
08/476,475 →
Enhanced Design and Process for a Conductive Adhesive
Patent:
6,534,724 →
Application:
08/864,044 →
Miniaturized Chip Scale Ball Grid Array Semiconductor Package
Patent:
6,429,530 →
Application:
09/184,839 →
Dielectric Interposer for Chip to Substrate Soldering
Patent:
6,657,313 →
Application:
09/233,385 →
Systems Interconnected by Bumps of Joining Material
Patent:
6,759,738 →
Application:
09/250,524 →
Silicon Packaging with Through Wafer Interconnects
Patent:
6,268,660 →
Application:
09/263,032 →
Micro grid array solder interconnection structure for second level packaging joining a module and a printed circuit board
Patent:
6,340,111 →
Application:
09/496,431 →
Lead-Free Solder Powder Material, Lead-Free Solder Paste and a Method for Preparing Same
Patent:
6,569,262 →
Application:
09/511,478 →
Solder bump forming method and apparatus
Patent:
6,273,328 →
Application:
09/521,354 →
Method and Structure of Column Interconnect
Patent:
6,495,917 →
Application:
09/527,276 →
Method for making interconnect for low temperature chip attachment
Patent:
6,340,630 →
Application:
09/536,557 →
Method and Apparatus for Forming Solder Bumps
Patent:
6,394,334 →
Application:
09/536,810 →
Method and Apparatus for Forming Solder Bumps
Patent:
6,527,158 →
Application:
09/537,228 →
Micro Grid Array Solder Interconnection Structure with Solder Columns for Second Level Packaging Joining a Module and Printed Circuit Board
High Density Column Grid Array Connections and Method Thereof
Patent:
6,429,388 →
Application:
09/564,110 →
Electrical interconnection package and method thereof
Patent:
6,333,563 →
Application:
09/587,944 →
Method for Enhancing Fatigue Life of Ball Grid Arrays
Patent:
6,283,359 →
Application:
09/644,486 →
Electronic Package Interconnect Structure Comprising Lead-Free Solders
Patent:
6,433,425 →
Application:
09/660,558 →
Electrochemical Etch for High Tin Solder Bumps
Patent:
6,468,413 →
Application:
09/697,333 →
Method of Forming Bga Interconnections Having Mixed Solder Profiles
Flip Chip C4 Extension Structure and Process
Lead Protective Coating Composition, Process and Structure Thereof
Lead-Free Solder Structure and Method for High Fatigue Life
Flip Chip C4 Extension Structure and Process
Interconnection Process for Module Assembly and Rework
Method of Interconnecting Electronic Components Using a Plurality of Conductive Studs
Solder Bump Forming Method and Apparatus
System on a Package Fabricated on a Semiconductor or Dielectric Wafer with Wiring on One Face, Vias Extending Through the Wafer, and External Connections on the Opposing Face
Rework Methods for Lead Bga/Cga
High Density Raised Stud Microjoining System and Methods of Fabricating the Same
High Density Area Array Solder Microjoining Interconnect Structure and Fabrication Method
Method of Forming a Lead-Free Tin-Silver-Copper Based Solder Alloy on an Electronic Substrate.
Patent:
6,596,621 →
Application:
10/151,075 →
Ball Grid Array Module and Method of Manufacturing Same
Electronic Package Interconnect Structure Comprising Lead-Free Solders
Bump Connection and Method and Apparatus for Forming Said Connection
Negative Volume Expansion Lead-Free Electrical Connection
Patent:
6,649,833 →
Application:
10/215,451 →
Ball Grid Array Package Construction with Raised Solder Ball Pads
Enhanced Design and Process for a Conductive Adhesive
Lead-Free Solder Powder Material, Lead-Free Solder Paste and a Method for Preparing Same
Ball Grid Array Rework Using a Continuous Belt Furnace
High Density Area Array Solder Microjoining Interconnect Structure and Fabrication Method
Compressible Films Surrounding Solder Connectors
Low Stress Conductive Polymer Bump
Flip Chip C4 Extension Structure and Process
Ball Limiting Metallurgy, Interconnection Structure Including the Same, and Method of Forming an Interconnection Structure
Interconnections for Flip-Chip Using Lead-Free Solders and Having Reaction Barrier Layers
Micro-Bumps to Enhance Lga Interconnections
Low Stress Conductive Polymer Bump
Techniques for Forming Interconnects
Patent:
7,348,270 →
Application:
11/625,449 →
Ball Grid Array Rework Using a Continuous Belt Furnace
Related Assignments
(1)
Other recorded transfers of the patents in this record — the chain of ownership.