IP Library Granted Patent US 11,415,809
Granted Patent B2
US 11,415,809 · App. 16/511,136 · Granted Aug 16, 2022

High-efficiency line-forming optical systems and methods using a serrated spatial filter

Inventor: Serguei Anikitchev (Hayward, CA)
Assignee: Veeco Instruments Inc.
G02B27/0983G02B19/0004G02B19/0047G02B27/0927G02B27/0988H01L21/268
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Quick Facts
Patent No.
US 11,415,809
App. No.
16/511,136
Granted
Aug 16, 2022
Kind
B2
Abstract

High-efficiency line-forming optical systems and methods that employ a serrated aperture are disclosed. The line-forming optical system includes a laser source, a beam conditioning optical system, a first aperture device, and a relay optical system that includes a second aperture device having the serrated aperture. The serrated aperture is defined by opposing serrated blades configured to reduce intensity variations in a line image formed at an image plane as compared to using an aperture having straight-edged blades.

Claims (19)

1. A method of performing defect annealing at a defect anneal temperature T D of a semiconductor wafer having a surface that includes a pattern, comprising:

forming from a CO 2 laser a light beam having a wavelength λ of 10.6 microns and a first intensity profile with a Gaussian distribution in at least a first direction;

passing at least 50% of the light beam in the first direction to form a first transmitted light;

focusing the first transmitted light at a Fourier plane to define a second intensity profile having a central peak and first side peaks immediately adjacent the central peak;

truncating the second intensity profile within each of the first side peaks with a serrated aperture disposed at the Fourier plane to define a second transmitted light that forms on the surface of the semiconductor wafer a first line image having between 1000 W and 3000 W of optical power and an intensity uniformity of within +/−5% over a first line length in the range from 5 mm to 100 mm; and

scanning the first line image over the surface of the semiconductor wafer to locally raise a temperature of the surface of the semiconductor wafer to the defect anneal temperature T D .

2. The method according to claim 1 , wherein the focusing of the first transmitted light is performed with a relay optical system having an optical component with a focal length f that defines the Fourier plane, wherein the serrated aperture has a width d2, and wherein the serrated aperture includes serrations having a length l in the range 0.1·(λ/(d2))·f≤l≤(λ/(d2))·f.

3. The method according to claim 2 , wherein the serrations have a pitch p within the range (0.9)·l≤p≤(1.1)·l.

4. The method according to claim 1 , wherein the defect anneal temperature T D is in the range 650° C.≤T D ≤1100° C.

5. The method according to claim 1 , further comprising performing spike annealing at a spike anneal temperature T A by:

forming a second line image at the surface of the semiconductor wafer using a second light beam having a second wavelength, wherein the second line image at least partially overlaps the first line image; and

scanning the second line image to locally raise the temperature of the surface of the semiconductor wafer from the defect anneal temperature T D to the spike anneal temperature T A .

6. The method according to claim 5 , wherein the spike anneal temperature T A is in the range 1100° C.≤T A ≤1350° C.

7. The method according to claim 5 , wherein the first line image has a first width and the second line image has a second width that is between 5% and 25% of the first width.

8. The method according to claim 7 , wherein the first width is in the range from 50 microns to 5 mm.

9. The method according to claim 5 , further comprising forming the second light beam using a laser diode light source and line-forming optics operably arranged relative thereto.

10. The method according to claim 5 , wherein the second wavelength is between 500 nm and 1000 nm.

11. The method according to claim 5 , wherein the second line image has a second line length in the range between 5 mm and 100 mm and an intensity uniformity of within +/−5%.

12. The method according to claim 5 , wherein the temperature of the surface of the semiconductor wafer has a variation from the spike anneal temperature T A due to pattern effects, and wherein the variation is no more than 60° C.

Assignments (5)
SECURITY INTEREST Recorded Feb 13, 2026
From: VEECO INSTRUMENTS INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 073780/0494 →
SECURITY INTEREST Recorded Jun 16, 2025
From: VEECO INSTRUMENTS INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 071649/0225 →
PATENT SECURITY AGREEMENT Recorded Dec 16, 2021
From: VEECO INSTRUMENTS INC.
To: HSBC BANK USA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 058533/0321 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2019
From: ULTRATECH, INC.
To: VEECO INSTRUMENTS INC.
Reel/Frame 051446/0476 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: ANIKITCHEV, SERGEUI
To: ULTRATECH, INC.
Reel/Frame 049749/0275 →