Silicon germanium heterojunction bipolar transistor structure and method
View Patent ↗Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
1. A method of forming a hetero-junction bipolar transistor
comprising:
providing a substrate;
forming a semiconductor collector layer on a first surface of said substrate, said semiconductor collector layer including a top surface and a bottom surface, said bottom surface being in contact with said substrate;
forming a heavily doped n-type collector pedestal within said semiconductor collector layer, said heavily doped n-type collector pedestal having an essentially uniform n-type dopant concentration of a first dopant from said bottom surface of said semiconductor collector layer to a depth below said top surface such that said essentially uniform n-type dopant concentration does not extend to said top surface;
removing defects at said top surface of said semiconductor collector layer by performing a laser anneal; and
forming a base layer on said top surface such that said base layer is doped with a p-type dopant, wherein the base layer is formed after forming the heavily doped n-type collector pedestal.
2. The method of claim 1 , wherein a peak concentration of said p-type dopant in said base layer adjacent to a bottom surface of said base layer is at least 100 times greater than a concentration of said p-type dopant in said semiconductor collector layer.
3. The method of claim 1 , wherein forming said base layer comprises epitaxially growing said base layer and in-situ doping said base layer such that a peak concentration of p-type dopant in said base layer is greater than approximately 1×10 19 cm −3 at approximately 0.03 μm above said top surface.
4. The method of claim 3 , wherein a concentration of p-type dopant in said semiconductor collector layer near said top surface is less than approximately 1×10 17 cm −3 .
5. The method of claim 1 , wherein, before said laser anneal, implanting said first dopant into said semiconductor collector layer at approximately 0.03 μm below said top surface to form said heavily doped n-type collector pedestal having said essentially uniform n-type dopant concentration of greater than approximately 1×10 18 cm −3 .
6. The method of claim 5 , said laser anneal being performed at temperatures greater than approximately 1100° C. and further being performed using a millisecond laser anneal process.
7. The method of claim 6 , wherein a diffusion of said first dopant being minimized such that a concentration profile of said first dopant outside of said heavily doped n-type collector pedestal decreases from approximately 1×10 18 cm −3 at approximately 0.02 μm below said top surface to less than approximately 1×10 17 cm −3 near said top surface.
8. The method of claim 5 , said p-type dopant comprising boron and said first dopant comprising one of phosphorous, antimony and arsenic.
9. The method of claim 1 , said bipolar transistor being formed with a current-gain cut-off frequency (F t ) of greater than approximately 365.00 GHz, a maximum oscillation frequency (F max ) of greater than approximately 255.00 GHz, a collector-base capacitance (Ccb) less than approximately 3.40 fF and a sheet base resistance (Rbb) less than approximately 110.00 Ohms.