Activating dopants using multiple consecutive millisecond-range anneals
View Patent ↗A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds.
1. A method of fabricating an integrated circuit, comprising:
providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and
subjecting at least a portion of the dopants to at least 3 consecutive laser anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds; and
wherein each anneal exposure comprises randomizing an exposure pattern of semiconductor substrate by multiple raster scanning passes in an arc-like fashion in which shifting subsequent passes by a laser beam are shifted with respect to previous passes.
2. The method of claim 1 , wherein the at least 3 consecutive laser anneal exposures are performed at a peak temperature of about 1100° C. to about 1350° C.
3. The method of claim 1 , further comprising annealing the source and drain extension regions prior to the at least 3 consecutive anneal exposures to cause the source and drain regions to extend laterally under sidewall surfaces of the gate conductor and to re-crystallize amorphous regions of the substrate.
4. The method of claim 3 , wherein said annealing is performed for a duration of greater than about 5 milliseconds.
5. The method of claim 1 , wherein the semiconductor substrate comprises single crystalline silicon.
6. The method of claim 5 , wherein an upper portion of the single crystalline silicon comprises threading dislocations and/or stacking faults having an area density that is equal to or less than about 10 5 cm −2 at a plane in the upper 10 to 20 micrometers of the silicon.
7. The method of claim 6 , wherein the semiconductor substrate is a silicon-on-insulator substrate.
8. The method of claim 1 , wherein the semiconductor substrate is a silicon-on-insulator substrate.