Semiconductor device and method of manufacturing semiconductor device
A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.
1. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM (Dynamic Random Access Memory) or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein a layer structure of said first sidewall is the same as a layer structure of said second sidewall.
2. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM (Dynamic Random Access Memory) or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over the substrate, said first gate electrode, and said second gate electrode;
forming said first sidewall and said second sidewall by etching said insulating forming a mask film that covers said second gate electrode and said second sidewall, and that does not cover said first gate electrode and said first sidewall;
narrowing the width of said first sidewall by performing etching using said mask film as a mask; and
removing said mask film.
3. The method of manufacturing the semiconductor device as set forth in claim 2 , further comprising:
forming said source and drain region of said first transistor by performing an ion implantation using said mask film, said first gate electrode, and said first sidewall as a mask, after said forming the mask film, and before said removing the mask film.
4. The method of manufacturing of the semiconductor device as set forth in claim 2 , wherein said narrowing the width of the first sidewall includes wet-etching said first sidewall, and, after said removing the mask film, the method further comprises:
forming an etching stopper film over said first transistor and said second transistor; and
forming an insulating interlayer over said etching stopper film.
5. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate a to insulating film and a first gate electrode of a first transistor which is included in circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM (Dynamic Random Access Memory) or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming the first sidewall and the second sidewall includes:
forming an insulating film used as a sidewall over said substrate, said first gate electrode, and said second gate electrode;
covering one of said insulating film located over said first gate electrode and said insulating film located over said second gate electrode by a first mask film, while not covering another one of said insulating film, by said first mask film;
forming one of said first sidewall and said second sidewall by etching said insulating film using said first mask film as a mask;
removing said first mask film;
covering said one of said first sidewall and said second sidewall by a second mask film, while not covering said another one of said insulating film located over said first gate electrode and said insulating film located over said second gate electrode by said second mask film; and
forming another of said first sidewall and said second sidewall by etching said insulating film using said second mask film as a mask.
6. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of, a second transistor which is included in a memory cell of a DRAM (Dynamic Random Access Memory) or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming the first sidewall and the second sidewall includes:
forming an insulating film used as a sidewall over said substrate, said first gate electrode, and said second gate electrode;
forming a portion of said second sidewall by etching said insulating film, while said insulating film remains in a sidewall of said first gate electrode;
covering said portion of said second sidewall and said second gate electrode by a mask film, while not covering said insulating film remaining in the sidewall of said first gate electrode by said mask film;
removing said insulating film remaining in the sidewall of said first gate electrode by etching using said mask film as a mask;
forming another insulating film used as a sidewall over said first gate electrode, said second gate electrode, and said portion of said second sidewall; and
forming another portion of said second sidewall by etching said another insulating film, and forming said first sidewall.
7. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate a first a insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating and a second gate electrode of a second transistor which is included in a memory cell of a DRAM (Dynamic Random Access Memory) or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode;
forming a source and drain region in each of said first transistor and said second transistor; and
after said forming the source and drain region in each of the first transistor and the second transistor:
forming an etching stopper film over said first transistor and said second transistor;
forming an insulating interlayer over said etching stopper film; and
forming a contact connected to said source and drain region in said insulating interlayer and said etching stopper film,
wherein at least a surface layer of said first sidewall is formed by a material different from said etching stopper film.
8. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM (Dynamic Random Access Memory) or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over said second gate electrode and in a periphery thereof;
forming another insulating film used as a sidewall over said second insulating film and said first gate electrode and in a periphery thereof; and
forming said first sidewall by etching said another insulating film located over said first gate electrode and in a periphery thereof, and forming said second sidewall by etching said second insulating film and said another insulating film located over the second insulating film.
9. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over the substrate, said first gate electrode, and said second gate electrode;
forming said first sidewall and said second sidewall by etching said insulating film;
forming a mask film that covers said second gate electrode and said second sidewall, and that does not cover said first gate electrode and said first sidewall;
narrowing the width of said first sidewall by performing etching using said mask film as a mask; and
removing said mask film.
10. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode;
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over the substrate, said first gate electrode, and said second gate electrode;
forming said first sidewall and said second sidewall by etching said insulating film;
forming a mask film that covers said second gate electrode and said second sidewall, and that does not cover said first gate electrode and said first sidewall;
narrowing the width of said first sidewall by performing etching using said mask film as a mask; and
removing said mask film; and
forming said source and drain region of said first transistor by performing an ion implantation using said mask film, said first gate electrode, and said first sidewall as a mask, after said forming the mask film, and before said removing the mask film.
11. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which is included in a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over the substrate, said first gate electrode, and said second gate electrode;
forming said first sidewall and said second sidewall by etching said insulating film;
forming a mask film that covers said second gate electrode and said second sidewall, and that does not cover said first gate electrode and said first sidewall;
narrowing the width of said first sidewall by performing etching using said mask film as a mask; and
removing said mask film, and
wherein said narrowing the width of the first sidewall includes wet-etching said first sidewall, and, after said removing the mask film, the method further comprising:
forming an etching stopper film over said first transistor and said second transistor; and
forming an insulating interlayer over said etching stopper film.
12. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of aid first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over the substrate, said first gate electrode, and said second gate electrode;
forming said first sidewall and said second sidewall by etching said insulating forming a mask film that covers said second gate electrode and said second sidewall, and that does not cover said first gate electrode and said first sidewall;
narrowing the width of said first sidewall by performing etching using said mask film as a mask; and
removing said mask film.
13. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode;
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over the substrate, said first gate electrode, and said second gate electrode;
forming said first sidewall and said second sidewall by etching said insulating film;
forming a mask film that covers said second gate electrode and said second sidewall, and that does not cover said first gate electrode and said first sidewall;
narrowing the width of said first sidewall by performing etching using said mask film as a mask; and
removing said mask film; and
forming said source and drain region of said first transistor by performing an ion implantation using said mask film, said first gate electrode, and said first sidewall as a mask, after said forming the mask film, and before said removing the mask film.
14. A method of manufacturing a semiconductor device, said method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell;
forming an extension region of said first transistor and an extension region of said second transistor;
forming a first sidewall in a sidewall of said first gate electrode;
forming a second sidewall having a larger width than that of said first sidewall in a sidewall of said second gate electrode; and
forming a source and drain region in each of said first transistor and said second transistor,
wherein said forming said first sidewall and said second sidewall includes:
forming an insulating film used as a sidewall over the substrate, said first gate electrode, and said second gate electrode;
forming said first sidewall and said second sidewall by etching said insulating film;
forming a mask film that covers said second gate electrode and said second sidewall, and that does not cover said first gate electrode and said first sidewall;
narrowing the width of said first sidewall by performing etching using said mask film as a mask; and
removing said mask film, and
wherein said narrowing the width of the first sidewall includes wet-etching said first sidewall, and, after said removing the mask film, the method further comprising:
forming an etching stopper film over said first transistor and said second transistor; and
forming an insulating interlayer over said etching stopper film.