Semiconductor memory device
A semiconductor memory device to an exemplary aspect of the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of column selectors, a common signal line pair including one common line commonly connected to one of each of the plurality of bit line pairs, and the other common line commonly connected to the other of each of the plurality of bit line pairs, a sense amplifier amplifying the potential difference of the common signal line pair, and a plurality of capacitance adding circuits that balance with parasitic capacitances of the column selectors which are not selected, the capacitance adding circuits being provided respectively between the one of each of the bit line pairs and the other common line and between the other of each of the bit line pairs and the one common line.
1. A semiconductor memory device comprising:
a plurality of memory cells arranged in a matrix;
a plurality of word lines each connected to the plurality of memory cells arranged in rows;
a plurality of bit line pairs each connected to the plurality of memory cells arranged in columns;
a plurality of column selectors each provided for the corresponding bit line pair;
a common signal line pair including one common line commonly connected to one of each of the plurality of bit line pairs, and the other common line commonly connected to the other of each of the plurality of bit line pairs;
a sense amplifier having an input terminal connected to the one common line, and the other input terminal connected to the other common line; and
a plurality of capacitance adding circuits that balance with parasitic capacitances of the column selectors which are not selected, the capacitance adding circuits being provided respectively between the one of each of the bit line pairs and the other common line and between the other of each of the bit line pairs and the one common line,
wherein the plurality of column selectors each comprise:
a first switch element provided between the one of the corresponding bit line pair and the one common line; and
a second switch element provided between the other of the corresponding bit line pair and the other common line,
the plurality of capacitance adding circuits corresponding to the column selectors each comprise:
a first capacitive element provided between the one of the corresponding bit line pair and the other common line; and
a second capacitive element provided between the other of the corresponding bit line pair and the one common line.
2. The semiconductor memory device according to claim 1 , wherein a parasitic capacitance value of each of the column selectors which are not selected and a capacitance value of each of the corresponding capacitance adding circuits are substantially equal to each other.
3. The semiconductor memory device according to claim 1 , wherein
a capacitance value of the first switch element in off state and a capacitance value of the first capacitive element are substantially equal to each other, and
a capacitance value of the second switch element in off state and a capacitance value of the second capacitive element are substantially equal to each other.
4. The semiconductor memory device according to claim 1 , wherein the first switch element and the second switch element are P-channel MOS transistors.
5. The semiconductor memory device according to claim 1 , wherein the first capacitive element and the second capacitive element are P-channel MOS transistors controlled to be off.
6. The semiconductor memory device according to claim 5 , wherein
the first switch element and the first capacitive element have substantially the same transistor size, and
the second switch element and the second capacitive element have substantially the same transistor size.
7. The semiconductor memory device according to claim 1 , wherein the first switch element and the second switch element are transfer gates each including a P-channel MOS transistor and an N-channel MOS transistor.
8. The semiconductor memory device according to claim 1 , wherein the first capacitive element and the second capacitive element are transfer gates each including a P-channel MOS transistor controlled to be off and an N-channel MOS transistor controlled to be off.
9. The semiconductor memory device according to claim 1 , further comprising a write control circuit that outputs write data to the common signal line pair.
10. A semiconductor memory devise comprising:
a plurality of memory cells arranged in a matrix;
a plurality of word lines each connected to the plurality of memory cells arranged in rows;
a plurality of bit line pairs each connected to the plurality of memory cells arranged in columns;
a pair of common lines including one common line connected to one of each of the plurality of bit line pairs, and the other common line connected to the other of each of the plurality of bit line pairs;
a sense amplifier connected to the pair of common lines;
a first switch element provided between one of a bit line pair of the plurality of bit line pairs and one of the pair of common lines;
a second switch element provided between the other one of the bit line pair and the other one of the pair of common lines;
a first capacitive element provided between one of the bit line pair and one of the pair of common lines; and
a second capacitive element provided between the other one of the bit line pair and the other one of the pair of common lines.
11. The semiconductor memory device according to claim 10 , wherein the first switch element and the second switch element are P-channel MOS transistors, and the first capacitive element and the second capacitive element are P-channel MOS transistors each having a gate connected to a power supply.
12. The semiconductor memory device according to claim 11 , wherein the first switch element and the second switch element, and the first capacitive element and the second capacitive element are P-channel MOS transistors having substantially the same size.