Method for a DMA-compatible peripheral
The invention relates to a method for organizing the registers of a peripheral in memory, the peripheral including at least one control register to be addressed in memory to store configuration data of the peripheral, one transmission register to be addressed in memory to store data to be transmitted from the memory to the peripheral, and one reception register to be addressed in memory to store data to be transmitted from the peripheral to the memory, the method including: duplicating, within a data memory range, the transmission/reception register to different contiguous addresses; and implementing in memory the control registers at contiguous addresses at the level of a memory range adjacent to the memory range where the transmission/reception register has been duplicated.
1. A method of operating a peripheral comprising a plurality of registers, the plurality of registers including a control register and a data register, the method comprising:
receiving a message and configuration data from a memory; and
storing the message in the data register and the configuration data in the control register, wherein the data register is provided both at a first address and a second address different from the first address, the first and second addresses being adjacent, wherein the control register is provided at a third address adjacent to the first address.
2. The method of claim 1 wherein receiving the message and configuration data comprises receiving, from a direct memory access controller, a data structure comprising the message and the configuration data.
3. A peripheral device, comprising:
a plurality of registers, the plurality of registers including a control register and a data register, wherein the data register is provided both at a first address and a second address different from the first address, the first and second addresses being adjacent, wherein the control register is provided at a third address adjacent to the first address, wherein a message and configuration data are received by the peripheral device from a memory, and wherein the message is stored in the data register and the configuration data is stored in the control register.
4. The peripheral device of claim 3 , further comprising an address decoder in communication with a direct memory access controller, wherein the address decoder partially decodes an address according to high-weight bits.
5. The method of claim 1 , wherein the peripheral is an SPI-type or LIN-type peripheral.
6. The peripheral device of claim 3 , wherein the peripheral device is an SPI-type or LIN-type peripheral device.