Method and structure of minimizing mold bleeding on a substrate surface of a semiconductor package
View Patent ↗A substrate surface of a semiconductor package, comprising: a plurality of product forming areas to provide mounting spaces of semiconductor chips. The substrate surface also comprises a plurality of staggered offset mesh block areas surrounding the plurality of product forming areas. The plurality of staggered offset mesh block areas minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.
1. A substrate surface of a semiconductor package, comprising:
a plurality of product forming areas to provide mounting spaces of semiconductor chips; and
a plurality of staggered offset mesh block areas surrounding the plurality of product forming areas to minimize mold bleeding from a mold cavity of the semiconductor package to outer areas of the substrate surface.
2. The substrate surface of claim 1 , further comprising a gap formed between two adjacent ones of the plurality of staggered offset mesh block areas to minimize a spread of the mold bleeding outside the gap.
3. The substrate surface of claim 2 , wherein a size of the gap is at most 0.5 millimeter.
4. The substrate surface of claim 2 , further comprising a sawline of the semiconductor package to form on the substrate surface below the gap.
5. The substrate surface of claim 4 , wherein the gap is approximately 0.04 millimeter deep.
6. The substrate surface of claim 1 , wherein the plurality of staggered offset mesh blocks are arranged to minimize a warpage of the substrate surface.
7. The substrate surface of claim 1 , wherein a mesh block of the plurality of staggered offset mesh block areas comprises at least one of a triangle, a rectangle, a pentagon, a heptagon, and an octagon.
8. The substrate surface of claim 1 , wherein the plurality of staggered offset mesh block areas are heat conductive to dissipate heat from semiconductor chips mounted on the substrate surface.
9. The substrate surface of claim 8 , wherein a mesh block of the plurality of staggered offset mesh block areas comprises copper.
10. The substrate surface of claim 1 , wherein the height of a mesh block of the plurality of staggered offset mesh block areas minimizes the flow of mold material to the outer area of the substrate surface.
11. The substrate surface of claim 10 , wherein the height is approximately 0.04 millimeters.
12. The substrate surface of claim 1 , wherein mesh blocks of the plurality of staggered offset mesh block areas comprises various sizes.
13. A substrate surface of a semiconductor package, comprising:
a plurality of product forming areas to provide mounting spaces of semiconductor chips; and
a dam structure on an outer area of the substrate surface of the semiconductor package, the dam structure comprising a plurality of mesh blocks;
a plurality of staggered offset mesh block areas surrounding the plurality of product forming areas to act as dam structures to block a flow of a mold material from a mold cavity of the semiconductor package to outer areas of the substrate surface.
14. The substrate surface of claim 13 , wherein the plurality of mesh blocks form a staggering pattern.
15. The substrate surface of claim 13 , further comprising a gap formed between the dam structure and a neighboring dam structure to minimize the flow of the mold material from the mold cavity to the outer area of the substrate surface.