Clock data recovery circuit and display device
A clock data recovery circuit has: a receiver circuit configured to receive a serial data including a predetermined pattern and to sample the serial data in synchronization with a clock signal to generate a sampled data; a PLL circuit configured to perform clock data recovery based on the sampled data to generate the clock signal; and a false lock detection circuit configured to detect false lock of the PLL circuit by detecting a false lock pattern included in the sampled data. The false lock pattern is a pattern obtained by the receiver circuit sampling the predetermined pattern when the false lock of the PLL circuit occurs.
1. A clock data recovery circuit comprising:
a receiver circuit configured to receive a serial data including a predetermined pattern and to sample said serial data in synchronization with a clock signal to generate a sampled data;
a PLL circuit configured to perform clock data recovery based on said sampled data to generate said clock signal; and
a false lock detection circuit configured to detect false lock of said PLL circuit by detecting that a false lock pattern is included in said sampled data,
wherein said false lock pattern is a pattern obtained by said receiver circuit sampling said predetermined pattern when said false lock of said PLL circuit occurs,
wherein said serial data is a video data signal supplied to a display driver for a display device,
wherein said video data signal comprises:
a video data corresponding to a video image displayed on said display device; and
a control data for controlling processing of said video data in said display driver, and
wherein said predetermined pattern is contained in said control data.
2. The clock data recovery circuit according to claim 1 , further comprising a frequency correction circuit configured to control, when said false lock is detected by said false lock detection circuit, said PLL circuit such that a frequency of said clock signal is reduced.
3. The clock data recovery circuit according to claim 2 ,
wherein said PLL circuit includes a voltage controlled oscillator configured to generate said clock signal whose frequency depends on an output voltage of a loop filter, and
wherein when said false lock is detected by said false lock detection circuit, said frequency correction circuit reduces said output voltage supplied to said voltage controlled oscillator.
4. The clock data recovery circuit according to claim 3 ,
wherein said false lock detection circuit comprises:
a first false lock detection circuit configured to detect first false lock that is said false lock at a first frequency higher than a desired frequency; and
a second false lock detection circuit configured to detect second false lock that is said false lock at a second frequency further higher than said first frequency,
wherein said frequency correction circuit reduces said output voltage greater when said second false lock is detected than when said first false lock is detected.
5. The clock data recovery circuit according to claim 1 ,
wherein said predetermined pattern is a training pattern inserted in said serial data for pull-in of said PLL circuit or for maintenance of a locked state of said PLL circuit.
6. The clock data recovery circuit according to claim 1 ,
wherein said false lock detection circuit is inactivated during a period of transferring said video data, and activated during a period of transferring said control data.
7. A display device comprising:
a display driver configured to drive a display panel; and
a control device configured to generate a video data signal being a serial data including a predetermined pattern and to transmit said video data signal to said display driver, wherein said display driver comprises:
a receiver configured to receive said video data signal and to sample said video data signal in synchronization with a clock signal to generate a sampled data;
a PLL circuit configured to perform clock data recovery based on said sampled data to generate said clock signal; and
a false lock detection circuit configured to detect false lock of said PLL circuit by detecting that a false lock pattern is included in said sampled data,
wherein said false lock pattern is a pattern obtained by said receiver sampling said predetermined pattern when said false lock of said PLL circuit occurs,
wherein said serial data is a video data signal supplied to a display driver for a display device,
wherein said video data signal comprises:
a video data corresponding to a video image displayed on said display device; and
a control data for controlling processing of said video data in said display driver, and
wherein said predetermined pattern is contained in said control data.
8. The display device according to claim 7 ,
wherein said display driver further comprises a frequency correction circuit, and
wherein when said false lock is detected by said false lock detection circuit, said frequency correction circuit controls said PLL circuit such that a frequency of said clock signal is reduced.
9. The display device according to claim 7 ,
wherein said predetermined pattern is a training pattern inserted in said video data signal for pull-in of said PLL circuit or for maintenance of a locked state of said PLL circuit.
10. The display device according to claim 7 ,
wherein said predetermined pattern is transmitted in a first period, and
said false lock detection circuit is activated during a predetermined period including said first period and deactivated during other than said predetermined period.