Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a plurality of bit lines;

a plurality of word lines wired in a direction intersecting said plurality of bit lines;

a source line corresponding to the plurality of word lines;

a memory cell array including a plurality of nonvolatile memory cells arranged to correspond with respective intersection points of said plurality of bit lines and said plurality of word lines, and respectively connected to said source line and to corresponding bit lines and word lines;

a program voltage generator that switches current supply capability to said source line based on the number of memory cells that are programmed at the same time, among said plurality of memory cells; and

a selection circuit that selects, among said plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by said program voltage generator.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein said program voltage generator comprises:

a plurality of program voltage generation circuits; and

a controller that controls, among said plurality of program voltage generation circuits, the number of program voltage generation circuits operated at the same time based on the number of memory cells that are programmed at the same time,

wherein said controller switches the current supply capability by controlling, among said plurality of program voltage generation circuits, the number of said program voltage generation circuits to be operated at the same time based on judging the number of said memory cells programmed at the same time by write data signals for said memory cells.

3. The nonvolatile semiconductor memory device according to claim 1 , said device being able to program multi-bit data in parallel, wherein

said program voltage generator comprises a controller that controls current supply capability for program voltage of said program voltage generator, based on the number of bits of logic “1” or the number of bits of logic “0”, among said multi-bit data.

4. The nonvolatile semiconductor memory device according to claim 1 , wherein

said selection circuit selects a bit line and a word line connected to said memory cell that is programmed, among said plurality of bit lines and said plurality of word lines.

5. The nonvolatile semiconductor memory device according to claim 1 , wherein said nonvolatile semiconductor memory device is a flash memory.

6. The nonvolatile semiconductor memory device according to claim 1 , in a case where logic “1” is programmed to at least all of said memory cells programmed at the same time, said program voltage generator is stopped.

7. A flash memory device comprising:

a plurality of bit lines;

a plurality of word lines wired in a direction intersecting said plurality of bit lines;

a source line corresponding to the plurality of word lines;

a flash memory cell array including a plurality of flash memory cells arranged to correspond with respective intersection points of said plurality of bit lines and said plurality of word lines, and respectively connected to said source line and to corresponding bit lines and word lines;

a plurality of switch transistors respectively connected between said plurality of bit lines and a reference potential, and whose ON-OFF states are controlled respectively by a plurality of write data signals respectively corresponding to said plurality of bit lines; and

a program voltage generator, to which said plurality of write data signals are connected and which supplies to said source line a capability of current in accordance with the number of said plurality of switch transistors turned ON by said plurality of write data signals.

8. The flash memory device according to claim 7 , wherein said program voltage generator comprises:

a plurality of program voltage generation circuits respectively connected to said source line, and

a controller that controls the number of program voltage generation circuits made to operate, among said plurality of program voltage generation circuits, by said plurality of write data signals.

9. The flash memory device according to claim 7 , wherein said program voltage generator comprises a charge pump circuit, said charge pump circuit including a booster capacitor and a rectifier element, an operation of each said charge pump circuit being controlled by said plurality of write data signals, wherein an output signal of said charge pump circuit is connected to said source line.

10. The flash memory device according to claim 8 , wherein each of said plurality of program voltage generation circuits comprises a charge pump circuit including a booster capacitor and a rectifier element, an operation of said charge pump circuit being controlled by said controller.

11. A nonvolatile semiconductor memory device comprising:

a plurality of bit lines;

a plurality of word lines wired in a direction intersecting said plurality of bit lines;

a source line corresponding to the plurality of word lines;

a memory cell array including a plurality of nonvolatile memory cells arranged to correspond with respective intersection points of said plurality of bit lines and said plurality of word lines, and respectively connected to said source line and to corresponding bit lines and word lines;

a program voltage generator which supplies to said source line a current outputted by said program voltage generator; and

a selection circuit that selects, among said plurality of memory cells, one or more memory cells that are programmed, to flow said current outputted by said program voltage generator,

wherein said program voltage generator comprises:

a plurality of program voltage generation circuits; and

a controller that controls, among said plurality of program voltage generation circuits, the number of program voltage generation circuits operated at the same time based on the number of memory cells that are programmed at the same time,

wherein performing said plurality of program voltage generation circuits flow a current to said memory cells.

12. The nonvolatile semiconductor memory device according to claim 11 , wherein said controller controls, among said plurality of program voltage generation circuits, the number of said program voltage generation circuits to be operated at the same time based on judging the number of said memory cells programmed at the same time by write data signals for said memory cells.

13. The nonvolatile semiconductor memory device according to claim 12 , said device being able to program multi-bit data in parallel, wherein

said controller controls the number of said program voltage generation circuits operated at the same time, based on the number of bits of logic “1” or the number of bits of logic “0”, among said multi-bit data.

14. The nonvolatile semiconductor memory device according to claim 12 , wherein said program voltage generation circuits comprise a charge pump circuit.

15. The nonvolatile semiconductor memory device according to claim 14 , wherein an operation of said charge pump circuit is controlled by said controller.

16. The nonvolatile semiconductor memory device according to claim 12 , said device being able to program multi-bit data in parallel, wherein

in a case where logic “1” is programmed to all of said multi-bit data, all of said plurality of program voltage generation circuits are stopped.

17. A nonvolatile semiconductor memory device comprising:

a plurality of bit lines;

a plurality of word lines wired in a direction intersecting said plurality of bit lines;

a source line corresponding to the plurality of word lines;

a memory cell array including a plurality of nonvolatile memory cells arranged to correspond with respective intersection points of said plurality of bit lines and said plurality of word lines, and respectively connected to said source line and to corresponding bit lines and word lines;

a program voltage generator that switches current supply capability to said source line based on the number of memory cells that are programmed at the same time, among said plurality of memory cells; and

a selection circuit that selects, among said plurality of memory cells, one or more memory cells that are programmed, to flow a current outputted by said program voltage generator,

wherein a total current outputted by said program voltage generator is based on which of the one or more the memory cells are selected.