Solar Cell
The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip thickness for division of the wafer into a plurality of strips, selecting a technique for cutting the wafer into the strips at an angle to the substantially planar surface, in which the combined strip thickness and width of wafer removed by the cutting is less than the thickness of the wafer, cutting the wafer into strips using the selected technique and separating the strips from each other.
1 . A bifacial solar cell comprising:
a individual semiconductor strip, of the order of 1 mm wide, comprising a semiconductor material of a first conductivity type, either p-type or n-type, the semiconductor strip having opposing front and rear faces and opposing first and second sides, wherein the front and rear faces are wider than the thickness of the strip, wherein the strip comprises a first doped layer of a second conductivity type in or on at least a portion of the front face and at least a portion of the first side;
a first metal contact in electrical contact with the first doped layer of the first side; and
a second metal contact in electrical contact with the second side.
2 . A bifacial solar cell as claimed in claim 1 , wherein the semiconductor strip is p-type, and the first doped layer is n-type.
3 . A bifacial solar cell as claimed in claim 1 , wherein the second metal contact is electrically isolated from the first doped layer.
4 . A bifacial solar cell as claimed in claim 2 , wherein the individual semiconductor strip is of p-type, wherein the first doped layer is of heavily doped n-type, at least a portion of the second side having a second doped layer, and wherein the second electrical contact is in electrical contact with the second doped layer.
5 . An individual bifacial solar cell as claimed in claim 1 , wherein the semiconductor strip is n-type, and the first doped layer is p-type.
6 . An individual bifacial solar cell as claimed in claim 5 , wherein the individual semiconductor strip is of lightly doped n-type semiconductor material, wherein the first doped layer is of heavily doped p-type, at least a portion of the second side having a second doped layer of heavily doped n-type, and wherein the second electrical contact is in electrical contact with the second doped layer.
7 . An individual bifacial solar cell as claimed in claim 1 , wherein the first doped layer is also in or on at least a portion of the rear face of the semiconductor strip.
8 . An individual bifacial solar cell as claimed in claim 1 , wherein the solar cell is textured.
9 . A bifacial solar cell as claimed in claim 8 wherein the solar cell is textured on the front and rear surfaces.
10 . An individual bifacial solar cell as claimed in claim 8 wherein the front and rear faces have a plurality of etch pits.
11 . A bifacial solar cell as claimed in claim 10 wherein the plurality of etch pits are each rounded in cross section.
12 . An individual bifacial solar cell as claimed in claim 10 , wherein the semiconductor is silicon, and wherein the silicon strip has been subjected to a texturing process comprising the steps of:
depositing a thin layer of silicon nitride onto the sidewalls of the silicon strip by low pressure chemical vapour deposition, said layer being sufficiently thin that it contains some holes through which the silicon is exposed;
etching the silicon strip in a suitable etchant to form etch pits up to several microns in size.
13 . An individual bifacial solar cell according to claim 10 , wherein each etch pit is rounded in cross-section.
14 . An individual bifacial solar cell as claimed in claim 1 , wherein the individual semiconductor strip has a thickness of 50 to 250 micrometers.
15 . An individual bifacial solar cell as claimed in claim 1 , wherein the individual semiconductor strip has a thickness of about 50 micrometers.
16 . An individual bifacial solar cell as claimed in claim 1 wherein the width of the face of the very narrow cell is at least 500 micrometers.
17 . An individual bifacial solar cell as claimed in claim 1 wherein the width of the face of the very narrow cell is between 500 and 1000 micrometers.
18 . An individual bifacial solar cell as claimed in claim 1 wherein the width of the face of the cell is of the order or 1 millimeter.
19 . An individual bifacial solar cell as claimed in claim 1 wherein the semiconductor strips are formed from single crystal silicon.
20 . An individual bifacial solar cell as claimed in claim 1 wherein the semiconductor strips are formed from multi-crystalline silicon.
21 . An individual bifacial solar cell as claimed in claim 1 wherein the semiconductor strips are bendable.
22 . A method of manufacturing a plurality of solar cells, comprising the steps of:
(a) forming a plurality of slots in a semiconductor wafer of a semiconductor material of a first conductivity type, either n-type or p-type, the slots extending at least partly through the wafer to create a plurality of semiconductor strips of the order of 1 mm wide, the semiconductor strips each having opposing front and rear faces and opposing first and second sides, wherein the front and rear faces are wider than the thickness of the strips;
b) fabricating a plurality of solar cells from said semiconductor strips; and
c) separating the semiconductor strips from the wafer to provide a plurality of individual bifacial solar cells.
23 . A method as claimed in claim 22 wherein the surfaces exposed by forming the plurality of slots in the wafer form the front and rear surfaces of the strips.
24 . A method as claimed in claim 22 wherein the solar cells are each bifacial solar cells.
25 . A method as claimed in claim 22 wherein the slots are formed in the wafer such that the thickness of the wafer is greater than the sum of the strip thickness and the slot width.
26 . A method as claimed in claim 22 wherein step (b) comprises:
(b1) introducing a first doped layer of a second conductivity type, either p-type or n-type, into or on at least a portion of the front face and at least a portion of the first side of the semiconductor strip;
(b2) depositing a first metal contact to the first doped layer of the first side so as to be in electrical contact therewith; and
(b3) depositing a second metal contact to the second side so as to be in electrical contact with the second side but not with the first doped layer.
27 . A method as claimed in claim 22 wherein, prior to step (a) the method comprises the step of introducing in or on one side of the wafer a doped layer of the first conductivity type.
28 . A method as claimed in claim 22 wherein, prior to step (a) the method comprises the step of introducing in or on a first side of the wafer a doped layer of the first conductivity type, being n-type or p-type, and introducing in or on a second side of the wafer a doped layer of the second conductivity type, being p-type or n-type respectively.
29 . A method as claimed in claim 22 wherein, prior to step (a) the method comprises introducing in or on one side of the wafer a doped layer having the second type.
30 . A method as claimed in claim 22 wherein, prior to step (a) the method comprises introducing an etch mask on one or both sides of the wafer.
31 . A method as claimed in claim 30 wherein the etch mask is patterned.
32 . A method as claimed in claim 30 wherein the etch mask comprises a stack formed of silicon dioxide and silicon nitride.
33 . A method as claimed in claim 22 , wherein the semiconductor wafer comprises a plurality of differently doped regions, wherein a first doped region of a first conductivity type, either n-type or p-type, has been introduced into or on one side of the wafer and a second doped region of a second conductivity type, either p-type or n-type respectively, has been introduced into or on the opposite side of the wafer, the second type being different from the first type.
34 . A method as claimed in claim 22 , wherein the slots are between 10 and 50 micrometers wide.
35 . A method as claimed in claim 22 , wherein the slots are less than 10 micrometers wide.
36 . A method as claimed in claim 22 , wherein narrow slots less than 10 micrometers wide are formed by photoelectrochemical etching.
37 . A method as claimed in claim 26 , wherein in step (b1), the first doped layer is introduced by diffusion of a suitable dopant.
38 . A method as claimed in claim 22 , wherein the semiconductor strips are of n-type conductivity, and the first doped layer is of p-type conductivity.
39 . A method as claimed in claim 22 , wherein the semiconductor strips are of p-type conductivity and the first doped layer is of n-type conductivity.
40 . A method as claimed in claim 26 , wherein the semiconductor strips are of lightly doped p-type conductivity, wherein, in step (b1) sufficient dopant is diffused into the first doped layer to yield a heavily doped n-type dopant region, the method comprising a further step (b1)(i) wherein a second doped layer of heavily doped p-type dopant region is provided by diffusion, using a p-type dopant, into at least a portion of the second side, and forming the second metal contact such that it is in electrical contact with the second doped layer.
41 . A method as claimed in claim 39 , wherein the first doped layer is, in addition to the front face and the first side, also formed on at least a portion of the rear face of each of the strips.
42 . A method as claimed in claim 22 , wherein
step a) comprises forming a plurality of parallel slots in the wafer to provide a plurality of semiconductor strips, each strip of the order of 1 mm wide formed from either a p-type or n-type semiconductor material and having opposing front and rear faces and opposing first and second sides, wherein the front and rear faces are wider than the thickness of the strip;
step b) comprises fabricating a bifacial solar cell from each of said plurality of strips; and
step c) comprises separating each of said plurality of strips from the wafer to provide a plurality of individual bifacial solar cells.
43 . A method according to claim 41 , wherein step (a) further comprises forming at least one interconnecting portion on or in said silicon wafer, said interconnecting portion connecting adjoining ones of said plurality of strips to maintain a substantially constant gap between said strips wherein said interconnecting portion is optionally one or more strips of said silicon wafer formed at least partly across one or both main surfaces thereof, said interconnecting portions being connected to each of said plurality of strips which are defined by said plurality of slots.
44 . A method as claimed in claim 22 wherein, in step (a), the plurality of slots are formed from both sides of the wafer.