Memory ordered store system in a multiprocessor computer system
A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.
1. A computer implemented method of storing data in a computer system, the storing comprising a store N and a store N+1, wherein store N is ordered to precede store N+1, the method comprising:
launching store N to a main memory of the computer system, store N comprising a request to store first data in the main memory;
initiating a first predetermined time period based on said launching of said store N;
launching store N+1 to a cache of the computer system based on an expiration of said first predetermined time period, store N+1 comprising a request to store second data in the cache;
determining, by said computer system, that said store N+1 achieves coherency; and,
canceling said store N+1 based on said store N+1 achieving coherency before said store N achieves coherency.
2. The method of claim 1 further comprising:
generating a send data response based on said store N being launched; and
initiating said first predetermined time period based on said send data response.
3. The method of claim 1 further comprising:
generating a command response based on said store N being launched; and
initiating said first predetermined time period based on said command response.
4. The method of claim 1 further comprising:
generating a combined send data and coherency response based on said store N+1 achieving coherency; and
determining that said store N+1 achieves coherency based on said combined send data and coherency response.
5. The method of claim 1 further comprising relaunching said canceled store N+1 based on an expiration of a second predetermined time period.
6. An apparatus for ordered storing of data in a computer system, the storing comprising a store N and a store N+1, wherein store N is ordered to precede store N+1, said apparatus comprising:
a main memory;
a cache; and
one or more controllers in communication with said main memory and said cache, said one or more controllers configured to perform a method comprising:
launching store N to the main memory, store N comprising a request to store first data in the main memory;
initiating a first predetermined time period based on said launching of said store N;
launching store N+1 to the cache based on an expiration of said first predetermined time period, store N+1 comprising a request to store second data in the cache;
determining, by said computer system, that said store N+1 achieves coherency; and,
canceling said store N+1 based on said store N+1 achieving coherency before said store N achieves coherency.
7. The apparatus of claim 6 , further comprising:
generating a send data response based on said store N being launched; and
initiating said first predetermined time period based on said send data response.
8. The apparatus of claim 6 , further comprising:
generating a command response based on said store N being launched; and
initiating said first predetermined time period based on said command response.
9. The apparatus of claim 6 , further comprising:
generating a combined send data and coherency response based on said store N+1 achieving coherency; and
determining that said store N+1 achieves coherency based on said combined send data and coherency response.
10. The apparatus of claim 6 further comprising relaunching said canceled store N+1 based on an expiration of a second predetermined time period.
11. A computer program product for executing a task in a computer system, the computer program product comprising:
a tangible non-transitory storage medium readable by a processing circuit and storing instructions comprising a store N and a store N+1, wherein store N is ordered to precede store N+1, for execution by the processing circuit for performing a method comprising:
launching store N to a main memory of the computer system, store N comprising a request to store first data in the main memory;
initiating a first predetermined time period based on said launching of said store N;
launching store N+1 to a cache of the computer system based on an expiration of said first predetermined time period, store N+1 comprising a request to store second data in the cache;
determining, by said computer system, that said store N+1 achieves coherency; and,
canceling said store N+1 based on said store N+1 achieving coherency before said store N achieves coherency.
12. The computer program product of claim 11 , further comprising:
generating a send data response based on said store N being launched; and
initiating said first predetermined time period based on said send data response.
13. The computer program product of claim 11 , further comprising:
generating a command response based on said store N being launched; and
initiating said first predetermined time period based on said command response.
14. The computer program product of claim 11 , further comprising:
generating a combined send data and coherency response based on said store N+1 achieving coherency; and
determining that said store N+1 achieves coherency based on said combined send data and coherency response.
15. The computer program product of claim 11 relaunching said canceled store N+1 based on an expiration of a second predetermined time period.
16. A computer implemented method storing data in a computer system, the storing comprising a store N and a store N+1, wherein store N is ordered to precede store N+1, the method comprising:
launching a store N to a main memory of the computer system, store N comprising a request to store first data in the main memory;
initiating, by the computer, a wait counter based on the launching of store N;
generating, by said computer, a finished counting signal based on said wait counter expiring;
launching a store N+1 to cache of the computer system based on receipt of said finished counting signal, store N+1 comprising a request to store second data in the cache; and,
canceling said store N+1 based on said store N+1 achieving coherency before said store N achieves coherency.
17. The method of claim 16 , further comprising setting a cancelled speculative latch in response to said canceling of said store N+1.
18. The method of claim 16 , further comprising setting a speculatively outstanding latch in response to said finished counting signal and when said store N has not achieved coherency.
19. The method of claim 16 further comprising, based on said store N achieving coherency before expiration of said wait counter, launching said store N+1 based on store N achieving coherency.
20. The method of claim 16 wherein:
generating a response comprising one of a send data response and a command response based on launching said store N; and,
initiating said wait counter based on said response being generated.