EDRAM macro disablement in cache memory
Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
1. A computer program product for embedded dynamic random access memory (EDRAM) macro disablement in a cache memory, comprising a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows;
iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro;
determining if an error occurred during the testing; and
disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
2. The computer program product of claim 1 , wherein the testing is an Array Built-in Self Test (ABIST).
3. The computer program product of claim 1 , wherein the method further comprises:
determining if an error overflow exists for EDRAM macro; and
activating a redundant circuit within the EDRAM macro based on the determining.
4. The computer program product of claim 3 , wherein determining if an overflow exists includes determining if there are redundant circuits within the EDRAM macro capable of circumventing the error within the EDRAM macro. .
5. The computer program product of claim 3 , wherein activating the redundant circuit within an EDRAM macro includes arranging circuit paths to circumvent the error inside the EDRAM macro.
6. The computer program product of claim 1 , wherein disabling write operations includes:
creating a logical bit mask, the logical bit mask including one bit representing each row of EDRAM macros of the cache memory bank;
setting a bit representing the row of EDRAM macros associated with the EDRAM macro within the logical bit mask; and
outputting the logical bit mask to least recently used (LRU) selection logic of the cache memory.
7. The computer program product of claim 6 , wherein disabling write operations further includes excluding a row of EDRAM macros represented by the bit from selection at the LRU selection logic.
8. A system for embedded dynamic random access memory (EDRAM) macro disablement in a cache memory, comprising:
a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros;
a cache memory control unit in communication with the cache memory bank, the cache memory control unit including a cache array mask register and a least recently used (LRU) selection logic unit, the cache memory control unit configured to perform a method, comprising:
isolating an EDRAM macro of the cache memory bank, the EDRAM macro being associated with one of the at least three rows;
iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro;
determining if an error occurred during the testing; and
disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
9. The system of claim 8 , wherein the testing is an Array Built-in Self Test (ABIST).
10. The system of claim 8 , wherein the method further comprises:
determining if an error overflow exists for EDRAM macro; and
activating a redundant circuit within the EDRAM macro based on the determining.
11. The system of claim 10 , wherein determining if an overflow exists includes determining if the EDRAM macro includes available internal redundant circuits capable of circumventing the error within the EDRAM macro.
12. The system of claim 10 , wherein activating the redundant circuit within an EDRAM macro includes arranging circuit paths to circumvent the error inside the EDRAM macro.
13. The system of claim 8 , wherein disabling write operations includes:
creating a logical bit mask at the cache array mask register, the logical bit mask including one bit representing each row of EDRAM macros of the cache memory bank;
setting a bit representing the row of EDRAM macros associated with the EDRAM macro within the logical bit mask; and
outputting the logical bit mask to the LRU selection logic unit.
14. The system of claim 13 , wherein disabling write operations further includes excluding a row of EDRAM macros represented by the bit from selection at the LRU selection logic.
15. A computer program product for embedded dynamic random access memory (EDRAM) macro disablement in a cache memory, comprising a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining if an EDRAM macro of a cache memory bank produces an error, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows;
correlating all error recovery operations for an entire row of EDRAM macros associated with the EDRAM macro; and
disabling write operations for the entire row based on the correlating.
16. The computer program product of claim 15 , wherein the correlating comprises determining a total number of error recovery operations for each EDRAM macro of the entire row, and determining if the total number of error recovery operations is above a predetermined threshold.