Methods for manufacturing enhancement-mode HEMTs with self-aligned field plate
View Patent ↗Various embodiments of the disclosure include the formation of enhancement-mode (e-mode) gate injection high electron mobility transistors (HEMT). Embodiments can include GaN, AlGaN, and InAlN based HEMTs. Embodiments also can include self-aligned P-type gate and field plate structures. The gates can be self-aligned to the source and drain, which can allow for precise control over the gate-source and gate-drain spacing. Additional embodiments include the addition of a GaN cap structure, an AlGaN buffer layer, AlN, recess etching, and/or using a thin oxidized AlN layer. In manufacturing the HEMTs according to present teachings, selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) can both be utilized to form gates.
1. A method of manufacturing an enhancement mode (e-mode) high electron mobility transistor (HEMT), comprising:
forming a first compound semiconductor layer over a surface of a substrate;
forming a second compound semiconductor layer over a surface of the first compound semiconductor layer opposite the substrate surface;
forming a first dielectric over a surface of the second compound semiconductor layer opposite the surface of the first compound semiconductor;
defining a source contact area, a drain contact area, and a gate contact area, through the first dielectric using one mask layer to expose portions of the second compound semiconductor layer;
forming a second dielectric conformally over the first dielectric and the exposed portions of the second compound semiconductor layer;
etching the second dielectric to expose the gate area;
isotropically etching the first dielectric exposed in the gate contact area to form an etched area;
growing epitaxial p-type second compound semiconductor on the exposed gate contact area to substantially fill the etched gate contact area and to cover at least a portion of the etched area of the first dielectric.
2. The method of claim 1 , further comprising:
masking the second dielectric to define the gate contact area.
3. The method of claim 2 , wherein masking further defines a field plate area.
4. The method of claim 1 , wherein etching the second dielectric further defines a lateral extension of an integrated field plate area.
5. The method of claim 1 , further comprising:
growing the epitaxial p-type second compound semiconductor to substantially fill the etched first dielectric area and to cover at least a portion of the second dielectric.
6. The method of claim 1 , further comprising:
forming an ohmic source contact over the source contact area;
forming an ohmic drain contact over the drain contact area; and
forming a Schottky metal over at least a portion of the epitaxial p-type second compound semiconductor.
7. The method of claim 6 , wherein the formed ohmic source contact further forms a field plate.
8. The method of claim 6 , wherein the formed Schottky metal further forms a field plate.
9. The method of claim 1 , wherein etching the second dielectric to expose the gate contact area further comprises:
recess etching at least a portion of the gate contact area through at least a portion of the second compound semiconductor layer.
10. The method of claim 1 , wherein the first compound semiconductor comprises GaN.
11. The method of claim 1 , wherein the substrate is selected from silicon, sapphire, silicon carbide, indium phosphide, diamond, silicon on diamond, and sapphire on diamond.
12. The method of claim 1 , further comprising:
forming an AlGaN layer between the surface of the substrate and the first compound semiconductor layer.
13. The method of claim 1 , wherein the second compound semiconductor layer comprises at least one of AlGaN, GaN, InP, and InAlN.
14. The method of claim 1 , wherein forming the second compound semiconductor layer, further comprises:
forming a compound semiconductor stack comprising at least two different compound semiconductors layers.
15. The method of claim 14 , wherein the semiconductor stack comprises an AlGaN layer and an AlN layer.
16. The method of claim 1 , wherein the first dielectric comprises a stack of dielectric layers.
17. The method of claim 1 , wherein forming the second dielectric further includes:
forming a plasma nitride as the second dielectric layer.
18. The method of claim 1 , further comprising:
forming a cap layer between the first dielectric layer and the second compound semiconductor layer, wherein the cap layer comprises a GaN layer.
19. The method of claim 1 , wherein forming the first dielectric further comprises:
forming multiple dielectric layers.
20. The method of claim 18 , further comprising:
forming an AlGaN layer between the substrate and the first compound layer.
21. A method of manufacturing an enhancement mode (e-mode) high electron mobility transistor (HEMT), comprising:
forming a GaN layer over a surface of a substrate;
forming a III-V semiconductor layer over a surface of the GaN layer opposite the substrate surface;
forming an AlN semiconductor layer between the III-V semiconductor layer and a first dielectric;
forming the first dielectric over a surface of the AlN semiconductor layer opposite the surface of the III-V semiconductor layer;
defining a source contact area, a drain contact area, and a gate contact area, through the first dielectric using one mask layer to expose the AlN semiconductor layer;
forming a second dielectric conformally over the first dielectric and the exposed portions of the AlN semiconductor layer;
etching the second dielectric to expose the AlN in the defined gate contact area; and
growing epitaxial p-type III-V semiconductor over the exposed gate contact area to substantially fill the etched gate contact area and to cover at least a portion of the etched first dielectric area.
22. The method of claim 21 , further comprising:
oxidizing the exposed AlN in the defined gate contact area to form a thin aluminum oxide layer; and
growing epitaxial p-type III-V semiconductor on the thin aluminum oxide layer in the defined gate contact area to substantially fill the defined gate area.
23. The method of claim 22 , wherein oxidizing the exposed AlN further comprises:
forming a thin oxidation layer of about 5 Å to about 120 Å.
24. The method of claim 22 , wherein the thin oxidation layer is about 10 Å to about 20 Å.
25. The method of claim 21 , wherein oxidizing the exposed AlN further comprises:
applying an oxidizing process selected from the group consisting of thermal oxidation, rapid thermal anneal, and plasma enhanced oxidation.
26. The method of claim 21 , further comprising:
growing the epitaxial p-type III-V semiconductor through at least a portion of the second dielectric.
27. The method of claim 21 , further comprising:
masking the second dielectric to define the gate contact area.
28. The method of claim 27 , wherein masking further defines a field plate area.
29. The method of claim 21 , wherein etching the second dielectric further defines a lateral extension of an integrated field plate area.
30. The method of claim 21 , further comprising:
growing the epitaxial p-type III-V semiconductor to substantially fill the etched first dielectric area and to cover at least a portion of the second dielectric.
31. The method of claim 21 , further comprising:
forming an ohmic source contact over the source contact area;
forming an ohmic drain contact over the drain contact area; and
forming a Schottky metal over at least a portion of the epitaxial p-type III-V semiconductor.
32. The method of claim 31 , wherein the formed ohmic source contact further forms a field plate.
33. The method of claim 31 , wherein the formed Schottky metal further forms a field plate.
34. The method of claim 21 , wherein etching the second dielectric to expose the gate contact area further comprises:
recess etching at least a portion of the gate contact area through at least a portion of the III-V semiconductor layer.
35. The method of claim 21 , wherein the substrate is selected from silicon, sapphire, silicon carbide, diamond, silicon on diamond, and sapphire on diamond.
36. The method of claim 21 , further comprising:
forming an AlGaN layer between the surface of the substrate and the GaN layer.
37. The method of claim 21 , wherein the III-V semiconductor layer comprises at least one of AlGaN, GaN, and InAlN.
38. The method of claim 21 , wherein the first dielectric comprises a stack of dielectric layers.
39. The method of claim 21 , wherein forming the second dielectric further includes:
forming a plasma nitride as the second dielectric layer.
40. The method of claim 21 , further comprising:
forming a cap layer between the first dielectric layer and the III-V semiconductor layer, wherein the cap layer comprises a GaN layer.
41. The method of claim 40 , further comprising:
forming an AlGaN layer between the substrate and the GaN layer.
42. The method of claim 21 , wherein forming the first dielectric further comprises:
forming multiple dielectric layers.
43. A method of manufacturing an enhancement mode (e-mode) high electron mobility transistor (HEMT), comprising:
forming a first compound semiconductor layer over a surface of a substrate;
forming a second compound semiconductor layer over a surface of the first compound semiconductor layer opposite the substrate surface;
forming a third compound semiconductor layer between the second compound semiconductor layer and a first dielectric;
forming the first dielectric over a surface of the third compound semiconductor layer opposite the surface of the second semiconductor layer;
defining a source contact area, a drain contact area, and a gate contact area, through the first dielectric using one mask layer to expose the AlN semiconductor layer;
forming a second dielectric conformally over the first dielectric and the exposed portions of the third compound semiconductor layer;
etching the second dielectric and a portion of the first dielectric to expose the third compound semiconductor in the defined gate contact area; and
growing epitaxial p-type second compound semiconductor over the exposed gate contact area to substantially fill the etched gate contact area and to cover at least a portion of the etched first dielectric area.
44. A method of manufacturing an enhancement mode (e-mode) high electron mobility transistor (HEMT), comprising:
forming a GaN layer over a surface of a substrate;
forming a III-V semiconductor layer over a surface of the GaN layer opposite the substrate surface;
forming an AlN semiconductor layer between the III-V semiconductor layer and a first dielectric;
forming the first dielectric over a surface of the AlN semiconductor layer opposite the surface of the III-V semiconductor layer;
defining a source contact area, a drain contact area, and a gate contact area, through the first dielectric using one mask layer to expose the AlN semiconductor layer;
forming a second dielectric conformally over the first dielectric and the exposed portions of the AlN semiconductor layer;
etching the second dielectric and a portion of the first dielectric to expose the AlN in the defined gate contact area; and
growing epitaxial p-type III-V semiconductor over the exposed gate contact area to substantially fill the etched gate contact area and to cover at least a portion of the etched first dielectric area.