SEMICONDUCTOR APPARATUS AND DATA READING METHOD
A semiconductor device includes multiple memory cells, a first and second digit lines, where either of them is coupled to the memory cell to be read, a sense amplifier having a first and second sense nodes that are respectively connected to the first and second digit lines, a first switch between the first digit line and the first sense node, a second switch between the second digit line and the second sense node, and a control circuit that outputs a first and second control signals for controlling a conducive state of the first and second switches. When an activation of the sense amplifier is started, the control circuit makes the first and second switches conductive and disconnects the first or second switch corresponding to the digit line to which the memory cell to be read is not connected according to a potential difference between the first and second sense nodes.
1 . A semiconductor device comprising:
a plurality of memory cells;
a first digit line and a second digit line, one of the first digit line and the second digit line being coupled to the memory cell to be read among the plurality of memory cells;
a sense amplifier including a first sense node and a second sense node that are respectively connected to the first digit line and the second digit line;
a first switch that is interposed between the first digit line and the first sense node;
a second switch that is interposed between the second digit line and the second sense node; and
a control circuit that outputs a first control signal and a second control signal for controlling a conducive state of the first switch and the second switch,
wherein at the time of starting an activation of the sense amplifier, the control circuit makes the first switch and the second switch conductive, and disconnects one of the first switch and the second switch corresponding to the digit line to which the memory cell to be read is not connected according to a potential difference between the first sense node and the second sense node.
2 . The semiconductor device according to claim 1 , wherein in a period of reading the memory cell to be read, the control circuit maintains the conductive state of the digit line to which the memory cell to be read is connected and one of the first switch and the second switch that corresponds the digit line.
3 . The semiconductor device according to claim 1 , wherein the control circuit controls the first switch and the second switch according to a word line selection control signal that activates a word line for selecting the memory cell to be read.
4 . The semiconductor device according to one of claims 1 , wherein the control circuit controls the first switch and the second switch according to time elapsed since the activation of the sense amplifier is started.
5 . The semiconductor device according to one of claims 1 , further comprising:
a first reading switch that is connected between the first sense node and a first reading node;
a second reading switch that is connected between the second sense node and a second reading node; and
a control circuit that outputs a reading control signal for controlling a conductive state of the first reading switch and the second reading switch,
wherein the reading control circuit makes the first reading switch and the second reading switch conductive in a period while one of the first switch and the second switch is disconnected.
6 . The semiconductor device according to one of claims 1 , wherein the memory cell is a memory cell in a DRAM.
7 . A method of reading data in a semiconductor device including a plurality of memory cells, a first digit line and a second digit line, one of the first digit line and the second digit line being coupled to the memory cell to be read among the plurality of memory cells, and a sense amplifier that includes a first sense node and a second sense node that are respectively connected to the first digit line and the second digit line, the method comprising:
at the time of starting an activation of the sense amplifier, connecting the first digit line and the second digit line to the first sense node and the second sense node and disconnecting one of the first digit line and the second digit line to which the memory cell to be read is not connected from the sense amplifier according to a potential difference between the first sense node and the second sense node.
8 . The method according to claim 7 , further comprising maintaining the connection state between the digit line which is connected to the memory cell to be read and one of the first sense node and the second sense node that corresponds to the digit line in a period of performing a reading operation of the memory cell to be read.
9 . The method according to claim 7 , further comprising controlling the connection between the first digit line and the second digit line to the sense amplifier according to a word line selection control signal that activates a word line to select the memory cell to be read.
10 . The method according to one of claims 7 , further comprising controlling the connection between the first digit line and the second digit line to the sense amplifier according to time elapsed since the activation of the sense amplifier is started.
11 . The method according to one of claims 7 , further comprising in a period of disconnecting one of the first digit line and the second digit line from the sense amplifier, transmitting a voltage of the first sense node to a first reading node and transmitting a voltage of the second sense node to a second reading node.
12 . The method according to one of claims 7 , wherein the memory cell is a memory cell in a DRAM.