Method and apparatus for training a memory signal via an error signal of a memory

1. A method comprising:

transmitting from a memory controller a command-address (C/A) signal to a memory module;

determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and

adjusting the C/A signal, in response to determining the error in the memory module, by delaying a phase of the C/A signal with respect to a clock signal, wherein adjusting is performed by the memory controller.

2. The method of claim 1 , wherein the error pin is a parity error pin of the memory module.

3. The method of claim 1 , wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.

4. The method of claim 1 , wherein the memory module is a Dual In-Line Memory Module (DIMM) with a Dynamic Random Access Memory (DRAM).

5. The method of claim 1 further comprises:

transmitting from the memory controller the adjusted C/A signal to the memory module.

6. The method of claim 5 , further comprising:

determining a phase setting for the C/A signal in response to determining the error in the memory module associated with the C/A signal and the adjusted C/A signal transmitted to the memory module; and

assigning the phase setting by the memory controller to the C/A signal with respect to the clock signal of the memory controller.

7. The method of claim 6 , wherein the phase setting is an average of phases of all correctly received C/A signals transmitted by the memory controller to the memory module, the received C/A signals including the C/A signal and the adjusted C/A signal.

8. The method of claim 1 , further comprising resetting by the memory controller an error register associated with the error in the memory module.

9. The method of claim 1 , further comprising modifying a control signal by the memory controller before modifying the C/A signal.

10. The method of claim 9 , wherein the control signal is a chip-select signal.

11. A memory controller comprising:

a transmitter operable to transmit a command-address (C/A) signal to a memory module; and

a training logic unit operable to:

determine by an error detection logic unit an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and

adjust the C/A signal, in response to determining the error in the memory module, by delaying a phase of the C/A signal with respect to a clock signal.

12. The memory controller of claim 11 , wherein the error pin is a parity error pin of the memory module.

13. The memory controller of claim 11 , wherein the memory module comprises a Double Data Rate 4 (DDR4) input-output interface.

14. The memory controller of claim 11 , wherein the memory module is a Dual In-Line Memory Module (DIMM) with a Dynamic Random Access Memory (DRAM).

15. The memory controller of claim 11 , wherein the transmitter is further operable to transmit the adjusted C/A signal to the memory module.

16. The memory controller of claim 15 , wherein the training logic unit is further operable to:

determine by a phase setting logic unit a phase setting for the C/A signal in response to determining the error in the memory module associated with the C/A signal and the adjusted C/A signal transmitted to the memory module; and

assign the phase setting to the C/A signal with respect to the clock signal.

17. The memory controller of claim 16 wherein the phase setting logic unit is further operable to compute an average of phases of all correctly received C/A signals transmitted by the memory controller to the memory module to determine the phase setting, the received C/A signals including the C/A signal and the adjusted C/A signal.

18. The memory controller of claim 11 further comprises a reset logic unit operable to reset an error register associated with the error in the memory module.

19. The memory controller of claim 11 , wherein the training logic unit is further operable to modify a control signal before modifying the C/A signal.

20. A system comprising:

a memory module having an error pin; and

a memory controller communicatively coupled to the memory module, the memory controller including:

a transmitter operable to transmit a command-address (C/A) signal to the memory module; and

a training logic unit operable to:

determine by an error detection logic unit an error in the memory module via an error signal from the error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and

adjust the C/A signal, in response to determining the error in the memory module, by delaying a phase of the C/A signal with respect to a clock signal.

21. The system of claim 20 , wherein the error pin is a parity error pin of the memory module.

22. The system of claim 20 , wherein the memory controller is communicatively coupled to the memory module via a Double Data Rate 4 (DDR4) input-output interface.

23. The system of claim 20 , wherein the memory module is a Dual In-Line Memory Module (DIMM) with a Dynamic Random Access Memory (DRAM).

24. The system of claim 20 , wherein the transmitter is further operable to transmit the adjusted C/A signal to the memory module.

25. The system of claim 23 , wherein the training logic unit is further operable to:

determine by a phase setting logic unit a phase setting for the C/A signal in response to determining the error in the memory module associated with the C/A signal and the adjusted C/A signal transmitted to the memory module; and

assign the phase setting to the C/A signal with respect to the clock signal.

26. The system of claim 25 , wherein the phase setting logic unit is further operable to compute an average of phases of all correctly received C/A signals transmitted by the memory controller to the memory module to determine the phase setting, the received C/A signals including the C/A signal and the adjusted C/A signal.

27. The system of claim 20 further comprises a reset logic unit operable to reset an error register associated with the error in the memory module.

28. The system of claim 20 , wherein the training logic unit is further operable to modify a control signal before modifying the C/A signal.