IP Library Assignment 054340/0280
Patent Assignment
Reel/Frame 054340/0280

Assignment of Assignor's Interest

Recorded: 2020-11-06 Pages: 12
Assignor
INTEL CORPORATION
Executed: 2020-07-23
Assignee
SONY CORPORATION
1-7-1 KONAN, MINATO-KU, TOKYO, JAPAN
Covered Properties (63)
Programmable Data Pattern for Repeated Writes to Memory
Application: 15/391,684 →
Publication: US 2018/0181344
Fast Boot Up Memory Controller
Application: 15/392,912 →
Publication: US 2018/0181336
Method and Apparatus for Natural Hand Visualization
Application: 15/692,856 →
Publication: US 2019/0066362
Reading from a Mode Register Having Different Read and Write Timing
Application: 15/721,052 →
Publication: US 2019/0103154
Apparatus and Method for Managing Subscription Requests for a Network Interface Component
Patent: 8,032,660 →
Application: 12/317,896 →
Publication: US 2010/0169507
Method and System for Error Management in a Memory Device
Patent: 8,862,973 →
Application: 12/634,286 →
Publication: US 2011/0138261
Method and System for Error Management in a Memory Device
Patent: 9,158,616 →
Application: 13/619,452 →
Publication: US 2013/0117641
Memory Interface Signal Reduction
Patent: 9,251,874 →
Application: 12/974,057 →
Publication: US 2012/0159059
Memory Interface Signal Reduction
Patent: 9,772,799 →
Application: 14/981,307 →
Publication: US 2016/0188258
Method and Apparatus for Training a Memory Signal via an Error Signal of a Memory
Patent: 8,533,538 →
Application: 12/824,675 →
Publication: US 2011/0320867
Silicon and Silicon Germanium Nanowire Structures
Patent: 9,129,829 →
Application: 14/274,592 →
Publication: US 2014/0326952
Silicon and Silicon Germanium Nanowire Structures
Patent: 9,595,581 →
Application: 14/789,856 →
Publication: US 2015/0303258
Silicon and Silicon Germanium Nanowire Structures
Application: 15/410,649 →
Publication: US 2017/0133462
Non-Planar Gate All-Around Device and Method of Fabrication Thereof
Patent: 8,987,794 →
Application: 13/997,118 →
Publication: US 2014/0225065
Non-Planar Gate All-Around Device and Method of Fabrication Thereof
Patent: 9,252,275 →
Application: 14/582,131 →
Publication: US 2015/0144880
Non-Planar Gate All-Around Device and Method of Fabrication Thereof
Application: 14/946,744 →
Publication: US 2016/0079422
Uniaxially Strained Nanowire Structure
Patent: 9,224,808 →
Application: 13/995,913 →
Publication: US 2014/0131660
Uniaxially Strained Nanowire Structure
Patent: 9,490,320 →
Application: 14/948,039 →
Publication: US 2016/0079360
Uniaxially Strained Nanowire Structure
Patent: 9,905,650 →
Application: 15/339,620 →
Publication: US 2017/0047405
Constrained Boot Techniques in Multi-Core Platforms
Patent: 9,552,039 →
Application: 14/125,497 →
Publication: US 2014/0115368
Tungsten Gates for Non-Planar Transistors
Patent: 9,177,867 →
Application: 13/993,330 →
Publication: US 2015/0041926
Tungsten Gates for Non-Planar Transistors
Patent: 9,637,810 →
Application: 14/860,336 →
Publication: US 2016/0035724
Tungsten Gates for Non-Planar Transistors
Patent: 9,580,776 →
Application: 14/860,341 →
Publication: US 2016/0035725
Tungsten Gates for Non-Planar Transistors
Patent: 9,812,546 →
Application: 15/401,965 →
Publication: US 2017/0117378
Tungsten Gates for Non-Planar Transistors
Application: 15/726,609 →
Publication: US 2018/0047825
Cmos Nanowire Structure
Patent: 9,224,810 →
Application: 13/996,503 →
Publication: US 2014/0197377
Cmos Nanowire Structure
Patent: 9,583,491 →
Application: 14/948,083 →
Publication: US 2016/0086951
Cmos Nanowire Structure
Application: 15/411,095 →
Publication: US 2017/0133277
Nanowire Transistor Devices and Forming Techniques
Patent: 9,012,284 →
Application: 13/560,531 →
Publication: US 2013/0161756
Nanowire Transistor Devices and Forming Techniques
Patent: 9,343,559 →
Application: 14/690,615 →
Publication: US 2015/0228772
Nanowire Transistor Devices and Forming Techniques
Patent: 9,812,524 →
Application: 15/155,806 →
Publication: US 2016/0260802
Variable Gate Width for Gate All-Around Transistors
Patent: 9,590,089 →
Application: 13/997,162 →
Publication: US 2013/0341704
Variable Gate Width for Gate All-Around Transistors
Application: 15/429,126 →
Publication: US 2017/0154960
Controlling An Asymmetrical Processor
Patent: 8,943,343 →
Application: 13/528,444 →
Publication: US 2013/0346771
Controlling an Asymmetrical Processor
Patent: 9,164,573 →
Application: 13/785,115 →
Publication: US 2013/0346778
Integration Methods to Fabricate Internal Spacers for Nanowire Devices
Patent: 9,859,368 →
Application: 15/333,123 →
Publication: US 2017/0047400
Integration Methods to Fabricate Internal Spacers for Nanowire Devices
Application: 15/859,226 →
Publication: US 2018/0122901
Integration Methods to Fabricate Internal Spacers for Nanowire Devices
Application: 16/153,456 →
Publication: US 2019/0051725
Integration Methods to Fabricate Internal Spacers for Nanowire Devices
Application: 16/358,613 →
Publication: US 2019/0214461
Leakage Reduction Structures for Nanowire Transistors
Patent: 9,825,130 →
Application: 13/996,845 →
Publication: US 2014/0264253
Nanowire Transistor with Underlayer Etch Stops
Patent: 9,064,944 →
Application: 13/996,848 →
Publication: US 2014/0264280
Nanowire Transistor with Underlayer Etch Stops
Patent: 9,385,221 →
Application: 14/688,647 →
Publication: US 2015/0221744
Nanowire Transistor with Underlayer Etch Stops
Patent: 9,614,060 →
Application: 15/173,890 →
Publication: US 2016/0284821
Nanowire Transistor Fabrication with Hardmask Layers
Application: 13/996,850 →
Publication: US 2015/0129830
Multi-Threshold Voltage Devices and Associated Techniques and Configurations
Patent: 9,761,713 →
Application: 14/941,291 →
Publication: US 2016/0155843
Multi-Threshold Voltage Devices and Associated Techniques and Configurations
Application: 15/377,994 →
Publication: US 2017/0092542
Techniques for Probabilistic Dynamic Random Access Memory Row Repair
Patent: 9,449,671 →
Application: 14/132,987 →
Publication: US 2014/0281206
Techniques for Probabilistic Dynamic Random Access Memory Row Repair
Application: 15/269,657 →
Publication: US 2017/0103795
Techniques for Determining Victim Row Addresses in a Volatile Memory
Patent: 9,269,436 →
Application: 14/133,011 →
Publication: US 2014/0281207
Techniques for Determining Victim Row Addresses in a Volatile Memory
Patent: 9,824,754 →
Application: 15/000,643 →
Publication: US 2016/0224262
Chip Arrangement and Method for Manufacturing a Chip Arrangement
Patent: 9,856,136 →
Application: 13/910,133 →
Publication: US 2014/0361387
Forcing Core Low Power States In A Processor
Patent: 9,495,001 →
Application: 13/972,569 →
Publication: US 2015/0058650
Forcing Core Low Power States In A Processor
Application: 15/296,096 →
Publication: US 2017/0102752
Subcarrier Allocations for Operation in Mixed Bandwidth Environments
Patent: 9,716,579 →
Application: 14/581,989 →
Publication: US 2016/0057754
Subcarrier Allocations for Operation in Mixed Bandwidth Environments
Application: 15/610,131 →
Publication: US 2018/0006793
Precharging and Refreshing Banks in Memory Device with Bank Group Architecture
Patent: 9,728,245 →
Application: 14/865,754 →
Publication: US 2016/0254044
Precharging and Refreshing Banks in Memory Device with Bank Group Architecture
Application: 15/639,725 →
Publication: US 2018/0025773
Memory Controller-Controlled Refresh Abort
Patent: 9,953,694 →
Application: 15/174,946 →
Publication: US 2017/0352406
Techniques for a Write Zero Operation
Patent: 9,804,793 →
Application: 15/277,182 →
Publication: US 2017/0255406
Techniques for a Write Zero Operation
Application: 15/788,679 →
Publication: US 2018/0136861
Techniques to Use Chip Select Signals for a Dual In-Line Memory Module
Application: 15/197,424 →
Publication: US 2017/0278562
Depth Image Provision Apparatus and Method
Application: 15/190,031 →
Publication: US 2017/0374352
Depth Image Provision Apparatus and Method
Application: 15/187,738 →
Publication: US 2017/0366801
Related Assignments (17)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Apr 23, 2009
From: SAHITA, RAVI; DURHAM, DAVID; RAGHUNATH, ARUN; RAMANUJAN, RAJ K.
To: INTEL CORPORATION
Reel/Frame 022587/0768 →
Assignment of Assignor's Interest Jan 8, 2010
From: BAINS, KULJIT S.; ZIMMERMAN, DAVID J.; BRZEZINSKI, DENNIS W.; WILLIAMS, MICHAEL
To: INTEL CORPORATION
Reel/Frame 023751/0944 →
Assignment of Assignor's Interest Jun 29, 2010
From: CHAUDHURI, SANTANU; SALMON, JOSEPH H.; BAINS, KULJIT S.
To: INTEL CORPORATION
Reel/Frame 024607/0338 →
Assignment of Assignor's Interest Feb 17, 2011
From: NALE, BILL
To: INTEL CORPORATION
Reel/Frame 025824/0052 →
Corrective Assignment to Correct the Parthasarathy Sarangam Spelling Is Correct by Added 4TH "a". Previously Recorded on Reel 022587 Frame 0768. Assignor(S) Hereby Confirms the Parthasarthy Sarangam Spelling Is Incorrect for First Name. Missing 4TH "A".. Aug 30, 2011
From: SAHITA, RAVI; DURHAM, DAVID; RAGHUNATH, ARUN; RAMANUJAN, RAJ K
To: INTEL CORPORATION
Reel/Frame 026826/0942 →
Assignment of Assignor's Interest Sep 16, 2013
From: CEA, STEPHEN M.; KIM, SEIYON; CAPPELLANI, ANNALISA
To: INTEL CORPORATION
Reel/Frame 031214/0193 →
Assignment of Assignor's Interest Jan 6, 2015
From: RACHMADY, WILLY; PILLARISETTY, RAVI; LE, VAN H.; KAVALIEROS, JACK T.
To: INTEL CORPORATION
Reel/Frame 034648/0208 →
Assignment of Assignor's Interest Jul 6, 2015
From: KUHN, KELIN J.; KIM, SEIYON; RIOS, RAFAEL; CEA, STEPHEN M.
To: INTEL CORPORATION
Reel/Frame 036002/0409 →
Assignment of Assignor's Interest Nov 24, 2015
From: RACHMADY, WILLY; PILLARISETTY, RAVI; LE, VAN H.; KAVALIEROS, JACK T.
To: INTEL CORPORATION
Reel/Frame 037136/0345 →
Assignment of Assignor's Interest Jan 12, 2017
From: TOMISHIMA, SHIGEKI; BAINS, KULJIT S.
To: INTEL CORPORATION
Reel/Frame 040971/0128 →
Assignment of Assignor's Interest Apr 24, 2017
From: LOVELACE, JOHN V.; MANDAVA, SREENIVAS; DAS, DEBALEENA
To: INTEL CORPORATION
Reel/Frame 042124/0811 →
Assignment of Assignor's Interest Apr 28, 2017
From: BAINS, KULJIT S.; ZIMMERMAN, DAVID J.; BRZEZINSKI, DENNIS W.; WILLIAMS, MICHAEL
To: INTEL CORPORATION
Reel/Frame 042172/0517 →
Assignment of Assignor's Interest Oct 31, 2017
From: COX, CHRISTOPHER E.; NALE, BILL
To: INTEL CORPORATION
Reel/Frame 043988/0669 →
Assignment of Assignor's Interest Aug 29, 2018
From: MANEVITCH, ALEXANDRA; GILAD, ITAMAR; VIENTE, KFIR; TAMIR, TAL
To: INTEL CORPORATION
Reel/Frame 046748/0161 →
Assignment of Assignor's Interest Sep 8, 2020
From: INTEL CORPORATION
To: SONY CORPORATION
Reel/Frame 053715/0428 →
Change of Name Jul 27, 2021
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 056998/0453 →
Change of Name Aug 24, 2021
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 057267/0844 →