Memory controller-controlled refresh abort
A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.
1. A memory controller, comprising:
input/output (I/O) circuitry to couple to a memory device; and
command logic to
issue a refresh command that is not a self-refresh command to a memory device for refresh of the memory device during active operation of the memory device, wherein issuance of the refresh command is to cause refresh of a group of N rows of the memory device, with refresh timing controlled by the memory controller and access timing being deterministic to the memory controller, wherein completion of the refresh includes refresh of all N rows, and wherein N is greater than one; and
issue a refresh abort to the memory device during the refresh, to cause the memory device to exit the refresh prior to completion of the refresh.
2. The memory controller of claim 1 , wherein N equals 8 or 16.
3. The memory controller of claim 1 , wherein the command logic to issue the refresh abort comprises issuance of a per bank abort command.
4. The memory controller of claim 1 , wherein the command logic to issue the refresh abort comprises issuance of an all bank abort command.
5. The memory controller of claim 4 , wherein the refresh command comprises a per bank refresh command and the refresh abort comprises an all bank abort command.
6. The memory controller of claim 1 , wherein the command logic to issue the refresh abort comprises the command logic to issue an Activate command.
7. The memory controller of claim 6 , wherein the command logic to issue the refresh abort comprises the command logic to specify an address for the refresh abort.
8. The memory controller of claim 1 , comprising the command logic to issue a mode register set (MRS) command prior to issuance of the refresh command, the MRS command to enable the memory device for refresh abort.
9. The memory controller of claim 1 , comprising the command logic to issue a subsequent refresh command after issuance of the refresh abort, the subsequent refresh command to cause refresh of the same N rows.
10. The memory controller of claim 1 , comprising the command logic to fail to issue a subsequent refresh command to cause refresh of the same N rows after issuance of the refresh abort.
11. The memory controller of claim 1 , wherein, in response to issuance of the refresh abort, the memory device is to not increment an internal refresh counter.
12. The memory controller of claim 1 , further comprising:
a scheduler communicatively coupled to the command logic.
13. The memory controller of claim 12 , wherein the scheduler is to
identify a scheduled memory access to the N rows; and
determine that access to a bank including the N rows has priority over refresh of the N rows; and
wherein the command logic is to issue the refresh abort to cancel refresh of the N rows to permit access to the bank.
14. The memory controller of claim 13 , wherein the scheduler is to determine that the access to the bank is to obviate a need to refresh the N rows, and wherein the command logic is to fail to subsequently refresh the N rows based on the determination.
15. The memory controller of claim 1 , wherein the memory device is to stagger a start of refresh of the N rows, wherein initiation of refresh of the N rows occurs one row at a time in sequence of increasing address.
16. The memory controller of claim 1 , wherein the memory device comprises a dynamic random access memory (DRAM) device compatible with a double data rate (DDR) standard.
17. The memory controller of claim 16 , wherein the memory device comprises a DDR5 (double data rate version 5) SDRAM (synchronous dynamic random access memory) device.
18. A system with a memory subsystem, comprising:
multiple dynamic random access memory (DRAM) devices; and
a memory controller coupled to the DRAM devices, the memory controller including command logic to
issue a refresh command that is not a self-refresh command to a memory device for refresh of the memory device during active operation of the memory device, wherein issuance of the refresh command is to cause refresh of a group of N rows of the memory device, with refresh timing controlled by the memory controller and access timing being deterministic to the memory controller, wherein completion of the refresh includes refresh of all N rows, and wherein N is greater than one; and
issue a refresh abort to the memory device during the refresh, to cause the memory device to exit the refresh prior to completion of the refresh.
19. The system of claim 18 , wherein the command logic to issue the refresh abort comprises issuance of a per bank abort command.
20. The system of claim 18 , wherein the command logic to issue the refresh abort comprises issuance of an all bank abort command.
21. The system of claim 18 , wherein the command logic to issue the refresh abort comprises the command logic to issue an Activate command.
22. The system of claim 18 , comprising the command logic to issue a mode register set (MRS) command prior to issuance of the refresh command, the MRS command to enable the memory device for refresh abort.
23. The system of claim 18 , the memory controller further comprising:
a scheduler communicatively coupled to the command logic, wherein the scheduler is to
identify a scheduled memory access to the N rows; and
determine that access to a bank including the N rows has priority over refresh of the N rows; and
wherein the command logic is to issue the refresh abort to cancel refresh of the N rows to permit access to the bank.
24. The system of claim 23 , wherein the scheduler is to determine that the access to the bank is to obviate the need to refresh the N rows, and wherein the command logic is to fail to subsequently refresh the N rows based on the determination.
25. The system of claim 18 , wherein the DRAM devices comprise double data rate version 5 (DDR5) SDRAM (synchronous dynamic random access memory) devices.
26. The system of claim 18 , further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to at least one processor;
a battery to power the system; or
a network interface communicatively coupled to at least one processor.
27. A method for managing memory refresh, comprising:
issuing a refresh command that is not a self-refresh command from a memory controller to a memory device for refresh of the memory device during active operation of the memory device, wherein the refresh command to cause refresh of a group of N rows with refresh timing controlled by the memory controller and access timing being deterministic to the memory controller, wherein completion of the refresh includes refresh of all N rows; and
issuing a refresh abort to the memory device during the refresh, to cause the memory device to exit the refresh prior to completion of the refresh.
28. The method of claim 27 , wherein issuing the refresh abort comprises issuing either a per bank abort command or an all bank abort command.
29. The method of claim 27 , further comprising:
identifying a scheduled memory access to the N rows; and
determining that access to a bank including the N rows has priority over refresh of the N rows; and
wherein issuing the refresh abort is to cancel refresh of the N rows to permit access to the bank.