Memory interface signal reduction
In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.
1. A controller comprising:
a single memory activate pin to provide a first signal;
one or more combined memory command/address signal pins; and
a selection circuit to:
interpret, if the first signal on the single memory activate pin is a first value, the first signal as a memory activate command, and second signals on the one or more combined memory command/address signal pins as memory address signals related to the memory activate command; and
interpret, if the first signal on the single memory activate pin is a second value, the first signal and the second signals as a memory command that is different than the memory activate command,
wherein, if the first signal is the second value, the second signals on respective combined memory command/address signals pins comprise a plurality of memory command signals.
2. The controller of claim 1 , wherein the controller comprises a processor, a Central Processing Unit, and/or a memory controller.
3. The controller of claim 1 , wherein the controller is adapted to be coupled to a Double Data Rate memory and the first signal or second signals are Double Data Rate signals.
4. The controller of claim 1 , wherein the controller is adapted to be coupled to a Double Data Rate 4 memory and the first signal or second signals are Double Data Rate 4 signals.
5. The controller of claim 4 , wherein the one or more combined memory command/address signal pins are CAS#/A 16 , RAS#/A 15 , and WE#/A 14 .
6. The controller of claim 1 , wherein, if the first signal is the second value, one of the second signals on a respective one of the combined memory command/address signal pins is a CAS, RAS and/or WE memory command signal.
7. The controller of claim 1 , wherein the one or more combined memory command/address signal pins are one or more lowest order memory address pins.
8. The controller of claim 1 , wherein the single memory activate pin is a dedicated pin to only receive the memory activate command.
9. A method comprising:
identifying a value of a first signal on a single memory activate pin configured to uniquely identify a memory activate command; and
interpreting, if the first signal on the single memory activate pin is a first value, the first signal as a memory activate command, and second signals on one or more combined memory command/address signal pins as memory address signals related to the memory activate command; and
interpreting, if the first signal on the single memory activate pin is a second value, the first signal and the second signals as a memory command that is different than the memory activate command,
wherein, if the first signal is the second value, the second signals on respective combined memory command/address signals pins comprise a plurality of memory command signals.
10. The method of claim 9 , wherein the first signal or second signals are Double Data Rate memory signals.
11. The method of claim 9 , wherein the first signal or second signals are Double Data Rate 4 memory signals.
12. The method of claim 11 , wherein the one or more combined memory command/address signal pins are CAS#/A 16 , RAS#/A 15 , and WE#/A 14 .
13. The method of claim 9 , further comprising interpreting, if the first signal is the second value, one of the memory command/address signal pins as CAS, RAS or WE memory command signal pins.
14. The method of claim 9 , wherein the one or more combined memory command/address signal pins are one or more lowest order memory address pins.
15. The method of claim 9 , wherein the single memory activate pin is a dedicated pin to only receive the memory activate command.