Nanowire transistor with underlayer etch stops
A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
1. A method of fabricating a nanowire transistor, comprising:
forming a fin structure having a first end and an opposing second end on a microelectronic substrate, wherein the fin structure comprises at least one sacrificial material layer alternating with at least one channel material layer;
forming a first underlayer etch stop structure to abut the fin structure first end;
forming a second underlayer etch stop structure to abut the fin structure second end;
forming a source structure proximate the fin structure first end, wherein the first underlayer etch stop structure is disposed between the source structure and the fin structure first end and disposed between the entire source structure and the microelectronic substrate; and
forming a drain structure proximate the fin structure second end, wherein the second underlayer etch stop structure is disposed between the drain structure and the at least one nanowire second end and disposed between the entire drain structure and the microelectronic substrate; and
selectively removing the at least one sacrificial material layer from the fin structure, wherein the remain at least one channel material layer forms at least one channel nanowire.
2. The method of claim 1 , further including forming a gate dielectric material abutting the at least one nanowire channel.
3. The method of claim 2 , further including forming a gate electrode material abutting the gate dielectric material.
4. The method of claim 1 , wherein the at least one nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are formed of the same material.
5. The method of claim 4 , wherein the at least one nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are formed of silicon germanium.
6. The method of claim 4 , wherein the at least one nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are formed of silicon.
7. A method of forming a computing device, comprising:
forming a board;
forming at least one component comprising:
forming a fin structure having a first end and an opposing second end on a microelectronic substrate, wherein the fin structure comprises at least one sacrificial material layer alternating with at least one channel material layer;
forming a first underlayer etch stop structure to abut the fin structure first end;
forming a second underlayer etch stop structure to abut the fin structure second end;
forming a source structure proximate the fin structure first end, wherein the first underlayer etch stop structure is disposed between the source structure and the fin structure first end and disposed between the entire source structure and the microelectronic substrate;
forming a drain structure proximate the fin structure second end, wherein the second underlayer etch stop structure is disposed between the drain structure and the at least one nanowire second end and disposed between the entire drain structure and the microelectronic substrate; and
selectively removing the at least one sacrificial material layer from the fin structure, wherein the remain at least one channel material layer forms at least one channel nanowire; and
attaching the at least one component to the board.
8. The method of claim 7 , further including forming a gate dielectric material abutting the nanowire channel between the nanowire channel first end and the nanowire channel second end.
9. The method of claim 8 , further including forming a gate electrode material abutting the gate dielectric material.
10. The method of claim 7 , wherein the at least one nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are formed of the same material.
11. The method of claim 10 , wherein the at least one nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are formed of silicon germanium.
12. The method of claim 10 , wherein the at least one nanowire channel, the first underlayer etch stop structure, and the second underlayer etch stop structure are formed of silicon.