Memory interface signal reduction
In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.
1. A memory apparatus comprising:
a memory activate contact to receive an activation command signal;
a plurality of address contacts to receive respective memory address signals;
a plurality of multi-function contacts; and
a selection circuit coupled to the memory activate contact and the plurality of multi-function contacts, wherein:
the selection circuit is to interpret signals on the multi-function contacts as additional memory address signals and to implement an activate command if the activation command signal has a first value; and
the selection circuit is to interpret the signals on the multi-function contacts as memory command signals if the activation command signal has a second value.
2. The memory apparatus of claim 1 , wherein the plurality of multi-function contacts includes three contacts.
3. The memory apparatus of claim 1 , wherein the memory command signals include a row address select (RAS) signal, a column address select (CAS) signal, and a write enable (WE) signal.
4. The memory apparatus of claim 1 , wherein the additional memory address signals include an A 14 address signal, an A 15 address signal, and an A 16 address signal.
5. The memory apparatus of claim 1 , wherein the selection circuit is to implement another memory command indicated by the signals on the multi-function contacts if the activation command signal has the second value.
6. The memory apparatus of claim 1 , further comprising a Double Data Rate 4 (DDR4) compliant memory coupled to the selection circuit to implement memory commands encoded by the memory command signals or the signals received on the multi-function contacts.
7. The memory apparatus of claim 1 , wherein the memory activate contact comprises a memory activate pin and the plurality of multi-function contacts comprise a plurality of multi-function pins.
8. A memory controller comprising:
a memory activate contact to provide an activation command signal to a memory;
a plurality of address contacts to provide respective memory address signals to the memory;
a plurality of multi-function contacts; and
a control circuit coupled to the memory activate contact and the plurality of multi-function contacts, wherein:
to indicate an activation command to the memory, the control circuit is to provide the activation command signal with a first value and provide respective additional memory address signals to the memory via the multi-function contacts; and
to indicate a memory command that is different from the activation command to the memory, the control circuit is to provide the activation command signal with a second value and provide respective memory command signals to the memory via the multi-function contacts to indicate the memory command.
9. The memory controller of claim 8 , wherein the plurality of multi-function contacts includes three contacts.
10. The memory controller of claim 8 , wherein the respective memory command signals include a row address select (RAS) signal, a column address select (CAS) signal, and a write enable (WE) signal.
11. The memory controller of claim 8 , wherein the respective additional memory address signals include an A 14 address signal, an A 15 address signal, and an A 16 address signal.
12. The memory controller of claim 8 , wherein the memory comprises a Double Data Rate 4 (DDR4) compliant memory.
13. The memory controller of claim 8 , wherein the memory controller is included on a same die as a processor to enable the processor to communicate with the memory.
14. The memory controller of claim 8 , wherein the memory controller is on a different die than a die of the memory.
15. The memory controller of claim 8 , wherein the memory activate contact comprise a memory activate pin and the plurality of multi-function contacts comprise a plurality of multi-function pins.
16. A system comprising:
a processor;
a memory; and
a memory controller to communicate memory commands to the memory using an activation command signal, a plurality of address signals, and a plurality of multi-function signals, wherein the memory is to interpret the multi-function signals as memory address signals or memory command signals based on whether the activation command signal has a first value or a second value, wherein:
to indicate an activation command to the memory, the memory controller is to provide the activation command signal with a first value and provide respective additional memory address signals to the memory as the multi-function signals; and
to indicate a memory command that is different from the activation command to the memory, the memory controller is to provide the activation command signal with a second value and provide respective memory command signals to the memory as the multi-function signals.
17. The system of claim 16 , wherein the plurality of multi-function signals includes three multi-function signals.
18. The system of claim 16 , wherein the memory command signals include a row address select (RAS) signal, a column address select (CAS) signal, and a write enable (WE) signal.
19. The system of claim 16 , wherein the respective additional memory address signals include an A 14 address signal, an A 15 address signal, and an A 16 address signal.
20. The system of claim 16 , wherein the memory is to receive the activation command signal and the plurality of multi-function signals via respective contacts.
21. The system of claim 16 , wherein the memory comprises a Double Data Rate 4 (DDR4) compliant memory.
22. The system of claim 16 , wherein the memory controller and the processor are included on a same die.
23. The system of claim 16 , wherein the memory controller is included in the processor.
24. The system of claim 16 , wherein the memory controller is on a separate die from the processor.
25. A method to be performed by a memory device, the method comprising:
receiving an activation command signal;
receiving a plurality of memory address signals;
receiving a plurality of multi-function signals;
interpreting the multi-function signals as additional memory address signals and performing an activate operation responsive to a determination that the activation command signal has a first value; and
interpreting the multi-function signals as memory command signals responsive to a determination that the activation command signal has a second value.
26. The method of claim 25 , wherein the activation command signal is received on an activation command contact of the memory device and the multi-function signals are received on respective multi-function contacts of the memory device.
27. The method of claim 25 , wherein the plurality of multi-function signals includes three multi-function signals.
28. The method of claim 25 , wherein the memory command signals include a row address select (RAS) signal, a column address select (CAS) signal, and a write enable (WE) signal.
29. The method of claim 25 , wherein the additional memory address signals include an A 14 address signal, an A 15 address signal, and an A 16 address signal.
30. The method of claim 25 , further comprising performing a memory operation other than the activate operation, as indicated by the multi-function signals, if the activation command signal has the second value.
31. The method of claim 25 , wherein the memory device comprises a Double Data Rate 4 (DDR4) compliant memory device.
32. A method to be performed by a memory controller, the method comprising:
providing an activation command signal with a first value to an activation command contact of a memory and providing a plurality of memory address signals to respective multi-function contacts of the memory to indicate an activation command to the memory; and
providing the activation command signal with a second value to the activation command contact and providing a plurality of memory command signals to the respective multi-function contacts to indicate a memory command that is different from the activation command to the memory.
33. The method of claim 32 , wherein the plurality of memory command signals includes three signals.
34. The method of claim 32 , wherein the memory command signals include a row address select (RAS) signal, a column address select (CAS) signal, and a write enable (WE) signal.
35. The method of claim 32 , wherein the memory address signals include an A 14 address signal, an A 15 address signal, and an A 16 address signal.
36. The method of claim 32 , wherein the memory comprises a Double Data Rate 4 (DDR4) compliant memory.