Constrained boot techniques in multi-core platforms
Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that controls which specific core(s) are to be powered up/down and/or which power state these core(s) need to enter based, at least in part, on input from OS and/or software application(s). Other embodiments are also claimed and disclosed.
1. A processor comprising:
a plurality of processor cores; and control logic, coupled to a first processor core and a second processor core of the plurality of processor cores, to detect a wake event from a low power consumption state and to cause the second processor core of the plurality of processor cores to enter a reduced power consumption state that consumes less power than a fully operational power consumption state, wherein, in response to the wake event, the control logic is to cause the first processor core to enter the fully operational power consumption state, wherein the control logic is to cause any remaining processor cores from the plurality of the processor cores, including the second processor core, to enter the reduced power consumption state based on a source of the wake event, wherein the first processor core is a bootstrap processor core and the second processor core is a non-bootstrap processor core.
2. The processor of claim 1 , wherein a third processor core of the plurality of processor cores is to enter the fully operational power consumption state in response to the wake event.
3. The processor of claim 1 , further comprising memory to store an operating system software, wherein the operating system software is to trigger the wake event.
4. The processor of claim 3 , wherein the operating system software is to trigger the wake event based on a timer.
5. The processor of claim 1 , wherein the control logic is to determine whether the second processor core is to enter the reduced power consumption state based on one or more of workload, scenario, and usage conditions present in a platform that comprises the processor.
6. The processor of claim 1 , wherein the low power consumption state comprises an idle state or a standby state.
7. The processor of claim 1 , further comprising memory to store an application software, wherein the application software is to trigger the wake event.
8. The processor of claim 7 , wherein the application software is to trigger the wake event based on a timer.
9. The processor of claim 1 , wherein the first processor core is to transmit at least one inter-processor interrupt to the second processor core in response to the wake event.
10. The processor of claim 1 , wherein the wake event is to indicate resumption from a platform idle state.
11. A method comprising: detecting a wake event from a low power consumption state at a first processor core of a processor; and cause a second processor core of the processor to enter a power consumption state that consumes less power than a fully operational power consumption state,
wherein, in response to the wake event, the first processor core is caused to enter the fully operational power consumption state, wherein any remaining processor cores from a plurality of the processor cores of the processor, including the second processor core, enters the reduced power consumption state based on a source of the wake event, wherein the first processor core is a bootstrap processor core and the second processor core is a non-bootstrap processor core.
12. The method of claim 11 , further comprising causing a third processor core of the processor to enter the fully operational power consumption state in response to the wake event.
13. The method of claim 11 , further comprising executing code to trigger the wake event.
14. The method of claim 11 , further comprising determining whether the second processor core is to enter the reduced power consumption state based on one or more of workload, scenario, and usage conditions present in a platform that comprises the processor.
15. The method of claim 11 , further comprising the first processor core transmitting at least one inter-processor interrupt to the second processor core in response to the wake event.
16. A computing system comprising:
memory to store an operating system software power management driver; and a processor, coupled to the memory, to execute the operating system software power management driver, the processor comprising:
a plurality of processor cores; and control logic coupled to a first processor core and a second processor core of the plurality of processor cores, to detect a wake event from a low power consumption state and to cause the second processor core of the plurality of processor cores to enter a power consumption state that consumes less power than a fully operational power consumption state,
wherein, in response to the wake event, the control logic is to cause the first processor core to enter the fully operational power consumption state, wherein the control logic is to cause any remaining processor cores from the plurality of the processor cores, including the second processor core, to enter the reduced power consumption state based on a source of the wake event, wherein the first processor core is a bootstrap processor core and the second processor core is a non-bootstrap processor core.
17. The system of claim 16 , wherein a third processor core of the plurality of processor cores is to enter the fully operational power consumption state in response to the wake event.
18. The system of claim 16 , wherein the operating system software power management driver is to trigger the wake event.
19. The system of claim 18 , wherein the operating system software power management driver is to trigger the wake event based on a timer.
20. The system of claim 16 , wherein the control logic is to determine whether the second processor core is to enter the reduced power consumption state based on one or more of workload, scenario, and usage conditions present in the computing system.
21. The system of claim 16 , wherein the low power consumption state comprises an idle state or a standby state.
22. The system of claim 16 , wherein the memory is to store an application software, wherein the application software is to trigger the wake event.
23. The system of claim 22 , wherein the application software is to trigger the wake event based on a timer.
24. The system of claim 16 , wherein the first processor core is to transmit at least one inter-processor interrupt to the second processor core in response to the wake event.
25. A non-transitory computer-readable medium to store instructions that when executed by a processor cause the processor to:
detect a wake event from a low power consumption state at a first processor core of the processor; and cause a second processor core of the processor to enter a power consumption state that consumes less power than a fully operational power consumption state,
wherein, in response to the wake event, the first processor core is caused to enter the fully operational power consumption state, wherein any remaining processor cores from a plurality of the processor cores of the processor, including the second processor core, is to enter the reduced power consumption state based on a source of the wake event, wherein the first processor core is a bootstrap processor core and the second processor core is a non-bootstrap processor core.
26. The computer-readable medium of claim 25 , wherein the instructions are to cause a third processor core of the processor to enter the fully operational power consumption state in response to the wake event.
27. The computer-readable medium of claim 25 , wherein the instructions are to cause the processor to execute code to trigger the wake event.
28. The computer-readable medium of claim 25 , wherein the instructions are to cause the first processor core to determine whether the second processor core is to enter the reduced power consumption state based on one or more of workload, scenario, and usage conditions present in a platform that comprises the processor.
29. The computer-readable medium of claim 25 , wherein the instructions are to cause the first processor core to transmit at least one inter-processor interrupt to the second processor core in response to the wake event.