Reading from a mode register having different read and write timing
A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.
1. A memory device, comprising:
a mode register to store configuration information to control operation of the memory device, wherein a write of configuration information directly to the mode register by a host takes less time than a read of the configuration information directly from the mode register by the host; and
a communication register separate from the mode register to provide data for a read of the configuration information by the host from the mode register, wherein in response to a request by the host to read the mode register, the mode register to copy the configuration information from the mode register to the communication register, to enable the host to read the configuration information from the communication register instead of directly from the mode register.
2. The memory device of claim 1 , wherein the mode register comprises a decision feedback equalization (DFE) configuration mode register.
3. The memory device of claim 1 , wherein the memory device is to receive a polling request from the host after request by the host to read the mode register, to determine if the communication register is ready to read.
4. The memory device of claim 1 , wherein the host is to read the configuration information from the communication register after a preset period of time.
5. The memory device of claim 1 , wherein the communication register is shared among multiple separate mode registers as a mailbox to read the configuration information in turn from the multiple separate mode registers.
6. The memory device of claim 5 , wherein the communication register comprises a portion write-only for the host, to enable the host to write address information to identify one of the multiple separate mode registers to copy configuration information to the communication register.
7. The memory device of claim 5 , wherein the communication register comprises a portion read-only for the host, to enable the host to read configuration information from one of the multiple separate mode registers.
8. A system to read memory device configuration information, comprising:
a memory controller; and
a memory device including
a mode register to store configuration information to control operation of the memory device, wherein a write of configuration information directly to the mode register by a host takes less time than a read of the configuration information directly from the mode register by the host; and
a communication register separate from the mode register to provide data for a read of the configuration information by the host from the mode register, wherein in response to a request by the host to read the mode register, the mode register to copy the configuration information from the mode register to the communication register, to enable the host to read the configuration information from the communication register instead of directly from the mode register.
9. The system of claim 8 , wherein the mode register comprises a decision feedback equalization (DFE) configuration mode register.
10. The system of claim 8 , wherein the memory device is to receive a polling request from the host after request by the host to read the mode register, to determine if the communication register is ready to read.
11. The system of claim 8 , wherein the host is to read the configuration information from the communication register after a preset period of time.
12. The system of claim 8 , wherein the communication register is shared among multiple separate mode registers as a mailbox to read the configuration information in turn from the multiple separate mode registers.
13. The system of claim 12 , wherein the communication register comprises a portion write-only for the host, to enable the host to write address information to identify one of the multiple separate mode registers to copy configuration information to the communication register.
14. The system of claim 12 , wherein the communication register comprises a portion read-only for the host, to enable the host to read configuration information from one of the multiple separate mode registers.
15. The system of claim 8 , further comprising one or more of:
at least one processor communicatively coupled to the memory controller;
a display communicatively coupled to at least one processor; or
a network interface communicatively coupled to at least one processor.
16. A method for reading configuration information in a memory device, comprising:
receiving a request from a host device to read a mode register that stores configuration information to control operation of the memory device, wherein a write of configuration information directly to the mode register by the host takes less time than a read of the configuration information directly from the mode register by the host device; and
copying the configuration information from the mode register into a communication register separate from the mode register to provide data for a read of the configuration information by the host in response to receiving the request, to enable the host to read the configuration information from the communication register instead of directly from the mode register.
17. The method of claim 16 , further comprising receiving a polling request from the host after receiving the request to read the mode register, and to indicate if the communication register is ready to read in response to polling request.
18. The method of claim 16 , comprising sharing the communication register among multiple separate mode registers as a mailbox to read the configuration information in turn from the multiple separate mode registers.
19. The method of claim 18 , wherein the communication register includes a portion write-only to the host device, and further comprising:
reading address information written to the write-only portion by the host device to identify one of the multiple separate mode registers; and
copying the configuration information to the communication register from the identified mode register in response to the request.
20. The method of claim 18 , wherein the communication register comprises a portion read-only for the host, and wherein copying the configuration information further comprises:
copying to the communication register in the read-only portion.
21. A memory controller, comprising:
a scheduler to generate an access request to a mode register of a memory device, wherein the mode register has discrepancy between a read delay and a write delay for direct read access and direct write access; and
input/output (I/O) hardware to access the mode register indirectly via a communication register instead of directly from the mode register.
22. The memory controller of claim 21 , wherein the access request comprises a read request, wherein a write of configuration information to the mode register takes less time than a read of the configuration information from the mode register.
23. The memory controller of claim 21 , wherein the access request comprises a write request, wherein a read of configuration information from the mode register takes less time than a write of the configuration information to the mode register.
24. The memory controller of claim 21 , wherein the scheduler is to generate a polling request after the access request, to determine if the communication register is ready to access.
25. The memory controller of claim 21 , wherein the communication register is shared among multiple separate mode registers as a mailbox to provide access to the multiple separate mode registers.