Memory arrays and memory devices
Strings of series-coupled memory cells selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional memory array architectures. Reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.
1. A memory array, comprising:
at least one string of series-coupled memory cells;
a first select gate coupled to a first memory cell of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells for selectively coupling the particular string of series-coupled memory cells to a bit line;
a second select gate coupled to a last memory cell of the particular string of series-coupled memory cells for selectively coupling the particular string of series-coupled memory cells to the bit line;
a first select line coupled to a control gate of the first select gate; and
a second select line coupled to a control gate of the second select gate;
wherein each memory cell of the particular string of series-coupled memory cells is located between the first select line and the second select line.
2. The memory array of claim 1 , wherein the at least one string of series-coupled memory cells comprises non-volatile memory cells.
3. The memory array of claim 1 , wherein the non-volatile memory cells comprise floating-gate memory cells.
4. The memory array of claim 1 , wherein the at least one string of series-coupled memory cells comprises at least one NAND string of memory cells.
5. The memory array of claim 1 , wherein the first select gate has a source/drain region connected to a source/drain region of the first memory cell, wherein the second select gate has a source/drain region connected to a source/drain region of the last memory cell, wherein the source/drain region of the first select gate is not connected to a source/drain region of any other memory cell, and wherein the source/drain region of the second select gate is not connected to a source/drain region of any other memory cell.
6. A memory array, comprising:
at least one string of series-coupled memory cells;
a first select gate coupled to a first memory cell of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells for selectively coupling the particular string of series-coupled memory cells to a bit line;
a second select gate coupled to a last memory cell of the particular string of series-coupled memory cells for selectively coupling the particular string of series-coupled memory cells to the bit line;
wherein the first select gate is adjacent the first memory cell; and
wherein the second select gate is adjacent the last memory cell.
7. The memory array of claim 6 , wherein the first select gate selectively couples only the particular string of series-coupled memory cells to the bit line and wherein the second select gate selectively couples only the particular string of series-coupled memory cells to the bit line.
8. The memory array of claim 6 , wherein the first select gate has a source/drain region connected to a source/drain region of the first memory cell, wherein the second select gate has a source/drain region connected to a source/drain region of the last memory cell, wherein the source/drain region of the first select gate is not connected to a source/drain region of any other memory cell, and wherein the source/drain region of the second select gate is not connected to a source/drain region of any other memory cell.
9. A memory array, comprising:
at least one string of series-coupled memory cells;
a first select gate coupled in series with a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells and comprising a first source/drain connected to a first end of the particular string of series-coupled memory cells and a second source/drain that is not directly connected to a source; and
a second select gate coupled in series with the particular string of series-coupled memory cells and comprising a first source/drain connected to an opposing end of the particular string of series-coupled memory cells and a second source/drain that is not directly connected to a source.
10. The memory array of claim 9 , wherein the first select gate is for selectively coupling a bit line to the first end of the particular string of series-coupled memory cells, and the second select gate is for selectively coupling the bit line to the opposing end of the particular string of series-coupled memory cells.
11. The memory array of claim 10 , wherein the first source/drain of the first select gate is connected to a first memory cell of the particular string of series-coupled memory cells, and wherein the first source/drain of the second select gate is connected to a last memory cell of the particular string of series-coupled memory cells.
12. The memory array of claim 9 , wherein each memory cell of the particular string of series-coupled memory cells is located between the first select gate and the second select gate.
13. The memory array of claim 9 , wherein each memory cell of the particular string of series-coupled memory cells is coupled in series with and is between the first select gate and the second select gate.
14. A memory array, comprising:
at least one string of series-coupled memory cells;
a first select gate comprising a first source/drain connected to a first end of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells and a second source/drain that is not directly connected to a source; and
a second select gate comprising a first source/drain connected to an opposing end of the particular string of series-coupled memory cells and a second source/drain that is not directly connected to a source; and
wherein the particular string of series-coupled memory cells is configured to be coupled to a bit line at the first end and the opposing end respectively by the first and second select gates during at least one access operation of the particular string of series-coupled memory cells.
15. A memory device, comprising:
at least one string of series-coupled memory cells;
a first select gate coupled to a first memory cell of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells and further coupled to a bit line; and
a second select gate coupled to a last memory cell of the particular string of series-coupled memory cells, and further coupled to the bit line;
wherein the memory device is configured to activate the first select gate during at least one access operation of the particular string of series-coupled memory cells; and
wherein the memory device is configured to activate the second select gate during at least one access operation of the particular string of series-coupled memory cells.
16. The memory device of claim 15 ,
wherein the first select gate comprises a first source/drain connected to the first memory cell and a second source/drain connected to the bit line, wherein the second source/drain of the first select gate is not directly connected to a source line; and
wherein the second select gate comprises a first source/drain connected to the last memory cell and a second source/drain connected to the bit line wherein the second source/drain of the second select gate is not directly connected to a source line.
17. The memory device of claim 15 , wherein the first select gate is adjacent the first memory cell, and wherein the second select gate is adjacent the last memory cell.
18. A memory device, comprising:
at least one string of series-coupled memory cells;
a first select gate coupled to a first memory cell of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells and further coupled to a bit line; and
a second select gate coupled to a last memory cell of the particular string of series-coupled memory cells, and further coupled to the bit line;
wherein the memory device is configured to activate the first select gate during at least one access operation of the particular string of series-coupled memory cells;
wherein the memory device is configured to activate the second select gate during at least one access operation of the particular string of series-coupled memory cells; and
wherein the memory device is further configured to concurrently activate the first select gate and the second select gate during at least one access operation of the particular string of series-coupled memory cells.
19. A memory device, comprising:
at least one string of series-coupled memory cells;
wherein a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells is selectively coupled to a bit line at a first end of the particular string of series-coupled memory cells;
wherein the particular string of series-coupled memory cells is selectively coupled to the bit line at an opposing end of the particular string of series-coupled memory cells; and
wherein the memory device is configured to concurrently couple both ends of the particular string of memory cells to the bit line during at least one access operation of the particular string of series-coupled memory cells.
20. A memory array, comprising:
at least one string of series-coupled memory cells;
a first select gate comprising a first source/drain connected to a first end of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells and a second source/drain that is not directly connected to a source; and
a second select gate comprising a first source/drain connected to an opposing end of the particular string of series-coupled memory cells and a second source/drain that is not directly connected to a source; and
wherein the particular string of series-coupled memory cells is configured to be coupled to a bit line at the first end and the opposing end respectively by the first and second select gates during at least one access operation of the particular string of series-coupled memory cells; and
wherein the particular string of series-coupled memory cells is configured to be coupled to the bit line at the first end and the opposing end respectively by the first and second select gates concurrently during at least a read operation of the particular string of series-coupled memory cells.
21. A memory device, comprising:
at least one string of series-coupled memory cells;
a first select gate coupled to a first memory cell of a particular string of series-coupled memory cells of the at least one string of series-coupled memory cells and further coupled to a bit line; and
a second select gate coupled to a last memory cell of the particular string of series-coupled memory cells, and further coupled to the bit line;
wherein the memory device is configured to activate the first select gate during at least one access operation of the particular string of series-coupled memory cells;
wherein the memory device is configured to activate the second select gate during at least one access operation of the particular string of series-coupled memory cells; and
wherein the memory device is configured to activate the first select gate and to activate the second select gate during a single access operation of the particular string of series-coupled memory cells.
22. The memory device of claim 21 , wherein the single access operation comprises a read operation.