IP Library Granted Patent US 8,810,002
Granted Patent B2
US 8,810,002 · App. 12/825,605 · Granted Aug 19, 2014

Vertical metal insulator metal capacitor

Inventors: Chewn-Pu Jou (Hsinchu, TW); Chen Ho-Hsiang (Hsinchu, TW); Fred Kuo (Hsinchu, TW); Tse-Hul Lu (Zhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
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Quick Facts
Patent No.
US 8,810,002
App. No.
12/825,605
Granted
Aug 19, 2014
Kind
B2
Abstract

A capacitor includes a first electrode. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The capacitor includes a second electrode. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures. The capacitor includes an insulating structure between the first electrode and the second electrode. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other thereby providing higher capacitance density.

Claims (38)

1. A capacitor, comprising:

a first electrode including a bottom conductive plane and a plurality of first vertical conductive structures, the bottom conductive plane being disposed over a substrate, wherein each first vertical conductive structure of the plurality of first vertical conductive structures comprises:

a plurality of first metal layers, wherein each first metal layer of the plurality of first metal layers is connected to an adjacent first metal layer of the plurality of first metal layers by a via, and the via and the adjacent first metal layer comprise a continuous metal filling;

a second electrode including a top conductive plane and a plurality of second vertical conductive structures; and

an insulating structure between the first electrode and the second electrode, a portion of the insulating structure is positioned between the first vertical conductive structures and the second vertical conductive structures,

wherein the plurality of first vertical conductive structures and the plurality of second vertical conductive structures are interlaced with each other and the insulating structure comprises another portion different from the portion between the first vertical conductive structures and the second vertical conductive structures, the portion between the first vertical conductive structures and the second vertical conductive structures comprising a material having a dielectric constant value greater than a dielectric constant value of the another portion of the insulating structure.

2. The capacitor of claim 1 , wherein the plurality of second vertical conductive structures comprise a plurality of second metal layers and a plurality of second via layers alternating with each other.

3. The capacitor of claim 1 , wherein the insulating structure includes a plurality of inter-metal dielectric layers.

4. The capacitor of claim 1 , wherein the plurality of first vertical conductive structures are distributed uniformly on the bottom conductive plane, and the plurality of second vertical conductive structures are distributed uniformly under the top conductive plane.

5. The capacitor of claim 1 , wherein the plurality of first vertical conductive structures are distributed in a square grid pattern on the bottom conductive plane, and the plurality of second vertical conductive structures are distributed in a square grid pattern under the top conductive plane.

6. An integrated circuit, comprising:

a substrate;

a dielectric layer on the substrate, the dielectric layer having a first dielectric constant value;

a plurality of metal layers;

a plurality of inter-metal dielectric layers; and

a capacitor comprising:

a first electrode including a bottom conductive plane and a plurality of first vertical conductive structures, wherein the bottom conductive plane is disposed over the substrate and in a first metal layer of the plurality of metal layers;

a second electrode including a top conductive plane and a plurality of second vertical conductive structures, wherein the top conductive plane is in a second metal layer of the plurality of metal layers, and the plurality of first vertical conductive structures and the plurality of second vertical conductive structures are interlaced with each other; and

an insulating structure between the first vertical conductive structures and the second vertical conductive structures, wherein the insulating structure includes portions of the plurality of inter-metal dielectric layers, the plurality of first vertical conductive structures include first portions of the plurality of metal layers between the first metal layer and the second metal layer, and the plurality of second vertical conductive structures include second portions of the plurality of metal layers between the first metal layer and the second metal layer, and the insulating structure having a second dielectric constant value greater than the first dielectric constant value,

wherein the insulating structure is a portion of the dielectric layer, and the dielectric layer is outside the capacitor.

7. The integrated circuit of claim 6 , wherein the plurality of first vertical conductive structures comprise the first portions of the plurality of metal layers and a plurality of first via layers alternating with each other, and the plurality of second vertical conductive structures comprise the second portions of the plurality of metal layers and a plurality of second via layers alternating with each other.

8. The integrated circuit of claim 6 , wherein the plurality of first vertical conductive structures are distributed uniformly on the bottom conductive plane and the plurality of second vertical conductive structures are distributed uniformly under the top conductive plane.

9. The integrated circuit of claim 6 , wherein the plurality of first vertical conductive structures are distributed in a square grid pattern on the bottom conductive plane, and the plurality of second vertical conductive structures are distributed in a square grid pattern under the top conductive plane.

10. A capacitor, comprising:

a first electrode including a bottom conductive plane and a plurality of first vertical conductive structures, the bottom conductive plane being disposed over a substrate, wherein each first vertical conductive structure of the plurality of first vertical conductive structures comprises:

a plurality of first metal layers, wherein each first metal layer of the plurality of first metal layers is connected to an adjacent first metal layer of the plurality of first metal layers by a via, and the via and the adjacent first metal layer comprise a continuous metal filling;

a second electrode including a top conductive plane and a plurality of second vertical conductive structures; and

an insulating structure between the first electrode and the second electrode, the insulating structure comprising a dielectric material having a dielectric constant greater than 2 between the first vertical conductive structures and the second vertical conductive structures,

wherein the plurality of first vertical conductive structures and the plurality of second vertical conductive structures are interlaced with each other, and the insulating structure comprises another portion different from the portion between the first vertical conductive structures and the second vertical conductive structures, the another portion of the insulating material different from the portion between the first vertical conductive structures and the second vertical conductive structures comprising a material having a dielectric constant value less than the dielectric constant value of the portion of the insulating structure between the first vertical structures and the second vertical structures.

11. The capacitor of claim 10 , wherein the plurality of second vertical conductive structures comprise a plurality of second metal layers and a plurality of second via layers alternating with each other.

12. The capacitor of claim 11 , wherein each via of the first plurality of via layers has a height ranging from 5000 Angstroms to 7000 Angstroms and each via layer of the second plurality of via layers has a height ranging from 5000 Angstroms to 7000 Angstroms.

13. The capacitor of claim 10 , wherein the insulating structure is a nitrogen-containing dielectric material.

14. The capacitor of claim 10 , wherein the insulating structure is a hydroxide-containing dielectric material.

15. The capacitor of claim 10 , wherein the plurality of first vertical conductive structures are distributed uniformly on the bottom conductive plane, and the plurality of second vertical conductive structures are distributed uniformly under the top conductive plane.

16. The capacitor of claim 10 , wherein the plurality of first vertical conductive structures are distributed in a square grid pattern on the bottom conductive plane, and the plurality of second vertical conductive structures are distributed in a square grid pattern under the top conductive plane.

17. The capacitor of claim 10 , wherein the plurality of first vertical conductive structures and the plurality of second vertical conductive structures comprise copper.

18. The capacitor of claim 1 , wherein the via has a height ranging from 5000 Angstroms to 7000 Angstroms.

19. The capacitor of claim 1 , wherein the insulating structure is a hydroxide-containing dielectric material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2010
From: JOU, CHEWN-PU; HO-HSIANG, CHEN; KUO, FRED; LU, TSE-HUL
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024608/0207 →
Continuity (2)
Provisional Application 61259787 · Nov 10, 2009
Related Publication 20110108950A1 · May 12, 2011