Method and system to improve the performance and/or reliability of a solid-state drive

1. An apparatus comprising:

logic to:

compress a block of data;

determine whether the block of data is compressed below a threshold, wherein the threshold is based on at least one of a size of the compressed block of data, and a ratio of a size of the block of data to a size of the compressed block of data; and

inform data selector logic to send a signal to a component to select the compressed block of data to cause a write of the compressed block of data into one or more memory modules in response to the determination that the block of data is compressed below the threshold.

2. The apparatus of claim 1 , wherein the logic is further to write the block of data into one or more memory modules without compression in response to a determination that the block of data is not compressed below the threshold.

3. The apparatus of claim 1 , wherein the logic is further to dynamically adjust a strength of an Error Correcting Code (ECC) of the block of data.

4. The apparatus of claim 3 , wherein the logic to dynamically adjust the strength of the ECC of the block of data is to dynamically adjust the strength of the ECC of the block of data based on at least one of a Bit Error rate (BER) associated with a location in the one or more memory modules that is to store the block of data and an erase count of a physical region that is to store the block of data.

5. The apparatus of claim 3 , wherein the logic to dynamically adjust the strength of the ECC of the block of data is to:

append a known data pad to the compressed block of data, wherein a combined size of the known data pad and the compressed block of data is to match a size of the block of data;

determine ECC check bytes of the compressed block of data and the known data pad; and

append the determined ECC check bytes to the compressed block of data and the known data pad.

6. The apparatus of claim 3 , wherein the compressed block of data comprises a plurality of code words and wherein the logic to dynamically adjust the strength of the ECC of the block of data is to:

determine a respective one of a plurality of ECC check bytes for each of the plurality of code words; and

append the determined respective one ECC check bytes to each of the plurality of code words.

7. The apparatus of claim 3 , wherein the compressed block of data comprises a plurality of code words and wherein the logic to dynamically adjust the strength of the ECC of the block of data is to:

append a respective one of a plurality of known data pads to each of the plurality of code words;

determine a respective one of a plurality of ECC check bytes for each of the plurality of code words and each respective one of the plurality of known data pads; and

append the determined respective one ECC check bytes to each code word and each respective one known data pad.

8. The apparatus of claim 3 , wherein the compressed block of data comprises a plurality of code words and wherein the logic to dynamically adjust the strength of the ECC of the block of data is to:

select one of the plurality of code words;

perform an exclusive OR (XOR) operation on all the code words except the selected code word to obtain a XOR code word; and

replace the selected code word with the XOR code word.

9. The apparatus of claim 1 , wherein the apparatus is a NAND flash memory solid-state drive (SSD) controller.

10. The apparatus of claim 1 , where the apparatus is compliant at least in part with an Open NAND Flash Interface (ONFI) protocol.

11. An apparatus comprising:

a component receiving raw data;

data selector logic to inform the component to select input from the received raw data or compressed data;

compression engine logic to:

compress the received raw data to produce a compressed block of data;

send the compressed block of data to the component;

determine whether the compressed block of data is compressed below a threshold;

inform the data selector logic to send a signal to the component to select the compressed block of data in response to determining that the compressed block of data is below the threshold, wherein the component selects the compressed block of data to forward the compressed block of data to one or more memory modules in response to receiving the signal to select the compressed block of data.

12. The apparatus of claim 11 , wherein the component comprises a multiplexer.

13. The apparatus of claim 11 , further comprising:

a memory controller wherein the component forwards the compressed block of data to the memory controller to write to the memory modules.

14. An apparatus, comprising:

logic to:

receive a block of data from a memory module

read a token associated with the received block of data to determine whether the received block of data is compressed;

send a decompression signal to a decompression engine to indicate to decompress the received block of data in response to the token indicating that the received block of data is compressed;

send a first select signal to a component to output decompressed data from the decompression engine for the received block of data.

15. The apparatus of claim 14 , wherein the logic is further to:

send a second select signal to the component to select to output the received block of data without being decompressed by the decompression engine in response to the token indicating that the received block of data is not compressed.

16. The apparatus of claim 14 , wherein the component comprises a multiplexer.

17. The apparatus of claim 14 , wherein the component and the decompression engine receive the block of data, wherein the decompression engine does not decompress the received block of data unless the decompression signal is sent to the decompression engine.