DRIVING CIRCUIT AND DRIVING METHOD

1 . A driving circuit comprising:

output buffers provided to drive first and second groups of data lines, which are connected with pixels of a display panel, with drive voltage signals supplied to input terminals of said output buffers, respectively;

first and second common portions;

a first short-circuiting section provided for each of the data lines of said first group to connect the input terminal of a corresponding one of said output buffers for said first group of data lines to said first common portion in response to a first connection control signal; and

a second short-circuiting section provided for each of the data lines of said second group to connect the input terminal of a corresponding one of said output buffers for said second group of data lines to said second common portion in response to a second connection control signal.

2 . The drive circuit according to claim 1 , further comprising:

a third short-circuiting section configured to connect said first and second common portions in response to a third connection control signal.

3 . The drive circuit according to claim 2 , further comprising:

a third common portion in addition to said first and second common portions; and

a fourth short-circuiting section configured to connect said first, second and third common portions in response to a fourth connection control signal.

4 . The drive circuit according to claim 2 , further comprising:

a gradation voltage generating section configured to generate first voltage signals of a first polarity, and second voltage signals of a second polarity different from the first polarity;

a voltage selecting section configured to select first drive voltage signals from said first voltage signals and second drive voltage signals from said second voltage signals based on an image data for one line of the display panel; and

a switching section configured to output said first and second drive voltage signals as drive voltage signals in response to first and second switching control signals such that said first and second drive voltage signals are outputted to said output buffers connected to said first and second group of data lines, or said first and second drive voltage signals are outputted to said output buffers connected to said second and first group of data lines, respectively.

5 . The drive circuit according to claim 4 , wherein said first and second switching control signals are activated during periods different from each other.

6 . The drive circuit according to claim 5 , wherein said first and second connection control signals are activated during a short-circuit period during which at least one of said first and second switching control signals is inactivated.

7 . The drive circuit according to claim 6 , wherein said third connection control signal is activated during a part of the short-circuit period during which said first and second switching control signals are both inactivated.

8 . The drive circuit according to claim 6 , further comprising:

a third common portion in addition to said first and second common portions; and

a fourth short-circuiting section configured to connect said first, second and third common portions in response to a fourth connection control signal,

wherein said third and fourth connection control signals are activated during a part of the short-circuit period during which said first and second switching control signals are both inactivated.

9 . A driving method comprising:

driving by output buffers, first and second groups of data lines, which are connected with pixels of a display panel, with drive voltage signals supplied to input terminals of said output buffers, respectively;

connecting the input terminal of each of said output buffers for said first group of data lines to a first common portion in response to a first connection control signal; and

connecting the input terminal of each of said output buffers for said second group of data lines to a second common portion in response to a second connection control signal.

10 . The drive method according to claim 9 , further comprising:

connecting said first and second common portions in response to a third connection control signal.

11 . The drive method according to claim 10 , further comprising:

connecting said first, second and third common portions in response to a fourth connection control signal.

12 . The drive method according to claim 10 , further comprising:

generating first voltage signals of a first polarity, and second voltage signals of a second polarity different from the first polarity;

selecting first drive voltage signals from said first voltage signals and second drive voltage signals from said second voltage signals based on an image data for one line of the display panel; and

outputting said first and second drive voltage signals as drive voltage signals in response to first and second switching control signals such that said first and second drive voltage signals are outputted to said output buffers connected to said first and second group of data lines, or said first and second drive voltage signals are outputted to said output buffers connected to said second and first group of data lines, respectively.

13 . The drive method according to claim 12 , further comprising:

activating said first and second switching control signals during periods different from each other.

14 . The drive method according to claim 13 , further comprising:

activating said first and second connection control signals during a short-circuit period during which at least one of said first and second switching control signals is inactivated.

15 . The drive method according to claim 14 , further comprising:

activating said third connection control signal during a part of the short-circuit period during which said first and second switching control signals are both inactivated.

16 . The drive method according to claim 14 , further comprising:

activating said third connection control signal and a fourth connection control signal during a part of the short-circuit period during which said first and second switching control signals are both inactivated; and

connecting said first and second common portions and a third common portion in response to the fourth connection control signal.