IP Library Patent Application 12826737
Patent Application
App. No. 12/826,737

SEMICONDUCTOR DEVICE

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Quick Facts
Patent No.
US None
App. No.
12/826,737
Abstract

After opening a via hole, the bottom portion and the top portion are rounded by etching performed twice. As a result, resistance of the via hole can be reduced and its quality and life can be enhanced.

Claims (34)

1 . A semiconductor device comprising:

an interconnection layer;

a silicon oxide layer laminated on the interconnection layer;

a via hole penetrating through the silicon oxide layer and reaching to the interconnection layer;

a barrier metal covering a whole surface in the via hole; and

a plug filled in the via hole,

wherein a top portion and a bottom portion of the via hole are rounded.

2 . The semiconductor device according to claim 1 , wherein a size of the top portion and the bottom portion in a direction of a depth of the plug is respectively among 5% to 15% to a depth of the plug.

3 . The semiconductor device according to claim 1 , wherein a size of the top portion and the bottom portion in a direction of a depth of the plug is respectively approximately 12% to a depth of the plug.

4 . The semiconductor device according to claim 1 , wherein the interconnection layer comprises:

an aluminum layer; and

a TiN (titanium nitride) film formed on the aluminum layer, and

the barrier metal is formed by Ti/TiN spattering applied to the whole surface in the via hole, and

the plug is formed by a tungsten.

5 . A manufacturing method of a semiconductor device comprising:

forming an interconnection layer;

forming a silicon oxide layer on the interconnection layer;

forming a via hole penetrating through the silicon oxide layer and reaching to the interconnection layer;

forming a barrier metal covering a whole surface in the via hole; and

forming a plug filled in the via hole,

wherein the forming the via hole comprises:

forming a rough profile of the via hole by dry etching;

trimming the via hole by RF (Radio Frequency) etching after the forming the rough profile; and

stopping the RF etching by a predetermined timing after the trimming.

6 . The manufacturing method of the semiconductor device according to claim 5 , wherein a size of the top portion and the bottom portion in a direction of a depth of the plug is respectively among 5% to 15% to a depth of the plug.

7 . The manufacturing method of the semiconductor device according to claim 5 , wherein a size of the top portion and the bottom portion in a direction of a depth of the plug is respectively approximately 12% to a depth of the plug.

8 . The manufacturing method of the semiconductor device according to claim 5 , wherein the interconnection layer comprises:

an aluminum layer; and

a TiN (titanium nitride) film formed on the aluminum layer, and

the forming the barrier metal comprises:

forming the barrier metal by Ti/TiN spattering applied to the whole surface in the via hole, and

the forming the plug comprises:

growing a tungsten film on a whole surface of the barrier metal in the via hole; and

applying CMP (Chemical Mechanical Polishing) to the tungsten film after the growing.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2010
From: OZAKI, YASUAKI; TOKUMINE, YOSHITAKE; MASUTOMO, TOORU; MATSUDA, TAKAHIRO
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024616/0680 →