ANALOG-DIGITAL CONVERTER CIRCUIT AND CALIBRATION METHOD
Provided is an analog-digital converter circuit having a normal mode for converting a received analog signal into a digital signal, and a calibration mode for adjusting an offset voltage of a comparator, the analog-digital converter including: a first comparator having a first analog signal input terminal supplied with an analog signal, and a first reference signal input terminal supplied with a first reference signal, in the normal mode; and a first calibration circuit that adjusts an offset voltage of the first comparator. In the calibration mode, assuming that a calibration resolution of the first calibration circuit is Δ 1 , a potential difference between a reference signal supplied to the first analog signal input terminal and a reference signal supplied to the first reference signal input terminal is n 1 Δ 1 +Δ 1 /2 (where n 1 is an integer).
1 . An analog-digital converter circuit having a normal mode for converting a received analog signal into a digital signal, and a calibration mode for adjusting an offset voltage of a comparator, the analog-digital converter comprising:
a first comparator having a first analog signal input terminal supplied with an analog signal, and a first reference signal input terminal supplied with a first reference signal, in the normal mode; and
a first calibration circuit that adjusts an offset voltage of the first comparator,
wherein, in the calibration mode, assuming that a calibration resolution of the first calibration circuit is Δ 1 , a potential difference between a reference signal supplied to the first analog signal input terminal and a reference signal supplied to the first reference signal input terminal is n 1 Δ 1 +Δ 1 /2 (where n 1 is an integer).
2 . The analog-digital converter circuit according to claim 1 , wherein the first calibration circuit comprises a digital-analog converter circuit.
3 . The analog-digital converter circuit according to claim 1 , further comprising:
a second comparator having a second analog signal input terminal supplied with the analog signal, and a second reference signal input terminal supplied with a second reference signal that is different from the first reference signal, in the normal mode; and
a second calibration circuit that adjusts an offset voltage of the second comparator,
wherein, in the calibration mode, assuming that a calibration resolution of the second calibration circuit is Δ 2 , a potential difference of a reference signal supplied to the second analog signal input terminal and a reference signal supplied to the second reference signal input terminal is n 2 Δ 2 +Δ 2 /2 (where n 2 is an integer).
4 . The analog-digital converter circuit according to claim 3 , wherein the second calibration circuit comprises a digital-analog converter circuit.
5 . The analog-digital converter circuit according to claim 3 , wherein, in the calibration mode, the first and second reference signals are calibrated to adjust offset voltages of the first and second comparators.
6 . The analog-digital converter circuit according to claim 3 , further comprising:
a first mode selection switch connected to the first analog signal input terminal; and
a second mode selection switch connected to the second analog signal input terminal.
7 . The analog-digital converter circuit according to claim 6 , wherein the first mode selection switch and the second mode selection switch are combined in a single switch.
8 . An analog-digital converter circuit having a normal mode for converting a received analog signal into a digital signal, and a calibration mode for adjusting an offset voltage of a comparator, the analog-digital converter circuit comprising:
a first comparator having a first analog signal input terminal supplied with an analog signal, and a first reference signal input terminal supplied with a first reference signal, in the normal mode; and
a first calibration circuit that adjusts an offset voltage of the first comparator,
wherein the first calibration circuit comprises:
a first main calibration unit that adjusts an offset adjustment amount so that an adjusted offset voltage has a value in a range of 0 to Δ 1 (where Δ 1 is a calibration resolution of the first calibration circuit); and
a first fine adjustment unit that shifts the offset adjustment amount by Δ 1 /2.
9 . The analog-digital converter circuit according to claim 8 , wherein the first calibration circuit comprises a digital-analog converter circuit.
10 . The analog-digital converter circuit according to claim 8 , wherein, in the calibration mode, the first analog signal input terminal and the first reference signal input terminal are short-circuited.
11 . The analog-digital converter circuit according to claim 8 , further comprising:
a second comparator having a second analog signal input terminal supplied with an analog signal, and a second reference signal input terminal supplied with a second reference signal that is different from the first reference signal, in the normal mode; and
a second calibration circuit that adjusts an offset voltage of the second comparator,
wherein the second calibration circuit comprises:
a second main calibration unit that adjusts an offset adjustment amount so that an adjusted offset voltage has a value in a range of 0 to Δ 2 (where Δ 2 is a calibration resolution of the second calibration circuit); and
a second fine adjustment unit that shifts the offset adjustment amount by Δ 2 /2.
12 . The analog-digital converter circuit according to claim 11 , wherein the second calibration circuit comprises a digital-analog converter circuit.
13 . The analog-digital converter circuit according to claim 11 , wherein, in the calibration mode, the second analog signal input terminal and the second reference signal input terminal are short-circuited.
14 . A calibration method that adjusts an offset voltage of a comparator by a calibration circuit having a calibration resolution A, the calibration method comprising:
fixing a potential difference applied to two input terminals of the comparator to nΔ+Δ/2 (where n is an integer);
changing a calibration signal supplied to the comparator from the calibration circuit; and
determining an offset adjustment amount based on an output signal output from the comparator.
15 . The calibration method according to claim 14 , wherein the calibration signal is generated by linear search.
16 . The calibration method according to claim 14 , further comprising:
holding, when the output signal from the comparator switches from a first level to a second level, a value of the calibration signal for a predetermined period of time, and counting the number of output signals having the second level; and
determining the offset adjustment amount based on the number of output signals.
17 . The calibration method according to claim 14 , wherein the calibration signal is generated by binary search.
18 . A calibration method that adjusts an offset voltage of a comparator by a calibration circuit having a calibration resolution A, the calibration method comprising:
causing two input terminals of the comparator to be short-circuited;
changing a calibration signal supplied to the comparator from the calibration circuit;
determining an offset adjustment amount based on an output signal output from the comparator; and
shifting the determined offset adjustment amount by Δ/2.
19 . The calibration method according to claim 18 , wherein the calibration signal is generated by linear search.
20 . The calibration method according to claim 18 , further comprising:
holding, when the output signal from the comparator changes from a first level to a second level, a value of the calibration signal for a predetermined period of time, and counting the number of output signals having the second level; and
determining the offset adjustment amount based on the number of output signals.
21 . The calibration method according to claim 18 , wherein the calibration signal is generated by binary search.