Semiconductor device with buried gate and method for fabricating the same
A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
1. A method for fabricating a semiconductor device, comprising:
forming a plurality of landing plugs over a substrate;
forming a trench by etching the substrate between the plurality of landing plugs;
forming a buried gate to partially fill the trench;
forming a gap-fill layer to gap-fill an upper side of the buried gate;
forming protruding portions of the plurality of landing plugs; and
trimming the protruding portions of the plurality of landing plugs.
2. The method of claim 1 , further comprising forming a contact hole to expose a respective one of the plurality of trimmed landing plugs.
3. The method of claim 2 , wherein forming the contact hole comprises forming both a bit line contact hole and a storage node contact hole.
4. The method of claim 1 , wherein the trimming of the protruding portions of the plurality of landing plugs comprises performing an isotropic etching process.
5. The method of claim 1 , wherein forming the plurality of landing plugs comprises forming a polysilicon layer.
6. The method of claim 1 , wherein the forming of the protruding portions of the plurality of landing plugs comprises recessing the gap-fill layer.
7. A method for fabricating a semiconductor device, comprising:
forming a plurality of landing plugs over a substrate;
forming a trench by etching the substrate between the plurality of landing plugs;
forming a buried gate to partially fill the trench;
forming a first gap-fill layer to gap-fill an upper side of the buried gate;
forming protruding portions of the plurality of landing plugs;
trimming the protruding portions of the plurality of landing plugs;
forming a spacer dielectric layer over an entire surface of the trimmed plurality of landing plugs;
forming a second gap-fill layer over the spacer dielectric layer; and
planarizing the second gap-fill layer and the spacer dielectric layer to expose the surfaces of the trimmed plurality of landing plugs.
8. The method of claim 7 , further comprising forming a contact hole to expose a surface a respective one of the plurality of landing plugs, after the planarizing of the second gap-fill layer and the spacer dielectric layer.
9. The method of claim 8 , wherein forming the contact hole to comprises forming both a bit Line contact hole and a storage node contact hole.
10. The method of claim 7 , wherein the trimming of the protruding portions of the plurality of landing plugs comprises performing an isotropic etching process.
11. The method of claim 7 , wherein forming the plurality of landing plugs comprises forming a polysilicon layer.
12. The method of claim 7 , wherein the forming of the protruding portions of the plurality of landing plugs comprises recessing the first gap-fill layer.