IP Library Patent Application 12827974
Patent Application
App. No. 12/827,974

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR TESTING THE SAME

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Quick Facts
Patent No.
US None
App. No.
12/827,974
Abstract

A semiconductor integrated circuit device includes: terminals 11 a and 11 m ; first to (2n+1)-th resistive elements (n is an integer of at least 1) (resistive element group 12 ) connected in series between the terminals 11 a and 11 m; a selection circuit 14 selecting, assuming that a terminal 11 a connected to one end of the first resistive element is a 0th node, a terminal 11 m connected to the other end of the (2n+1)-th resistive element is a (2n+1)-th node, and a connection point of the other end of an i-th resistive element (i is an integer from 1 to 2n) and one end of an (i+1)-th resistive element is an i-th node, any one of the 0th to (2n+1)-th nodes and outputting a voltage applied to the selected node; a switch group 15 a capable of shorting any 2k-th node (k is an integer from 0 to n); and a switch group 15 b capable of shorting any (2k+1)-th node. The 2k-th and (2k+1)-th nodes are shorted, and subsequently, a predetermined voltage is temporarily applied between the terminals 11 a and 11 m.

Claims (18)

1 . A semiconductor integrated circuit device, comprising:

first and second terminals;

first to (2n+1)-th resistive elements (n is an integer of at least 1) connected in series between the first and second terminals;

a selection circuit selecting, assuming that a first terminal connected to one end of the first resistive element is a 0th node, a second terminal connected to the other end of the (2n+1)-th resistive element is a (2n+1)-th node, and a connection point of the other end of an i-th resistive element (i is an integer from 1 to 2n) and one end of an (i+1)-th resistive element is an i-th node, any one of the 0th to (2n+1)-th nodes and outputting a voltage applied to the selected node;

a first switch group capable of shorting any 2k-th node (k is an integer from 0 to n); and

a second switch group capable of shorting any (2k+1)-th node.

2 . The semiconductor integrated circuit device according to claim 1 , wherein the first and second switch groups are open in a normal operation mode and are temporarily shorted in a test mode.

3 . The semiconductor integrated circuit device according to claim 1 , further comprising a plurality of the selection circuits, wherein wirings, each extending from a corresponding one of the 0th to (2n+1)-th nodes, extend in parallel to each other to branch points of the plurality of selection circuits.

4 . The semiconductor integrated circuit device according to claim 3 , wherein the plurality of the selection circuits are arranged under a plurality of wiring arrangement regions in output cell arrangement regions.

5 . A method for testing a semiconductor integrated circuit device comprising:

first and second terminals and first to (2n+1)-th resistive elements (n is an integer of at least 1) connected in series between the first and second terminals and capable of selecting, assuming that a first terminal connected to one end of a first resistive element is a 0th node, a second terminal connected to the other end of the (2n+1)-th resistive element is a (2n+1)-th node, and a connection point of the other end of an i-th resistive element (i is an integer from 1 to 2n) and one end of an (i+1)-th resistive element is an i-th node, any one of the 0th to (2n+1)-th nodes and outputting a voltage applied to the selected node, the method comprising:

(a) shorting any 2k-th node (k is an integer from 0 to n), that is, all the even-numbered nodes and any (2k+1)-th node, that is, all the odd-numbered nodes, termed “step (a)”;

(b) temporarily applying a predetermined voltage between the first and second terminals, termed “step (b)”; and

(c) opening any 2k-th node, that is, all the even-numbered nodes and any (2k+1)-th node, that is, all the odd-numbered nodes, termed “step (c)”.

6 . The method for testing the semiconductor integrated circuit device according to claim 5 , further comprising (d) measuring electrical characteristics of the first to (2n+1)-th resistive elements after step (c), termed “step (d)”.

7 . The method for testing the semiconductor integrated circuit device according to claim 6 , further comprising:

(a0) measuring initial electrical characteristics of the first to (2n+1)-th resistive elements before step (a), termed “step (a0)”; and

(e) comparing measurement results of the electrical characteristics obtained in steps (a0) and (d) after step (d), termed “step (e)”.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2010
From: KIDOKORO, TORU
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024642/0569 →