Methods and apparatus for extending the effective thermal operating range of a memory
Apparatus and systems are provided for thermal regulation of a memory integrated circuit (“IC”). The apparatus and systems may include a thermal sensor on a memory IC, and a heating element coupled to the thermal sensor. The heating element is adapted to heat the memory IC in response to a signal from the thermal sensor. Other aspects are also provided.
1. A memory integrated circuit (“IC”) comprising:
a control circuit that provides a first output signal when a temperature of the memory IC is above a predetermined temperature, and a second output signal when the temperature of the memory IC is below the predetermined temperature;
a heating element adapted to heat the memory IC when the control circuit provides the second output signal; and
a memory cell comprising a diode designed to operate above the predetermined temperature.
2. The memory IC of claim 1 , wherein the control circuit comprises a temperature transducer that provides an output signal proportional to temperature.
3. The memory IC of claim 2 , wherein the temperature transducer comprises one or more of a current output temperature sensor, a voltage output sensor, a Brokaw cell, a bi-polar junction transistor-based temperature sensor, a thermocouple, a resistance temperature device, and a thermistor.
4. The memory IC of claim 2 , wherein the control circuit further comprises a resistor coupled to the temperature transducer.
5. The memory IC of claim 2 , wherein the control circuit further comprises an operational amplifier having a first input terminal coupled to the temperature transducer, and a second input terminal coupled to a reference voltage.
6. The memory IC of claim 5 , wherein the control circuit further comprises a resistor coupled to the first input terminal of the operational amplifier.
7. The memory IC of claim 1 , wherein the heating element comprises a resistive heating element.
8. The memory IC of claim 1 , wherein the heating element comprises a plurality of resistive heating elements.
9. The memory IC of claim 1 , further comprising a enable/disable circuit adapted to disable the control circuit when the memory IC operates in a low power mode.
10. The memory IC of claim 1 , further comprising a enable/disable circuit adapted to enable the control circuit when the memory IC operates under line power, and to disable the control circuit when the memory IC operates under battery power.
11. The memory IC of claim 1 , further comprising a enable/disable circuit adapted to enable the control circuit when the memory IC: (1) exhibits a predetermined number of read errors; (2) operates in an error recovery mode; and/or (3) operates in a safe mode.
12. The memory IC of claim 1 , further comprising a circuit adapted to delay access to the memory IC until the memory IC operates in a predetermined temperature range.
13. The memory IC of claim 1 , wherein the memory IC comprises a three-dimensional memory array.