Analog multiplexer circuits and methods
A sample and hold circuit is disclosed that provides longer hold times. An analog multiplexer circuit is also disclosed that exhibits low switch leakage. The analog multiplexer circuit comprises a shared node, a plurality of input circuits, a control input for selecting one or more of the plurality of input circuits, and an amplifier coupled to the shared node. Each input circuit comprises an input node, a primary input switch for selectively coupling an input to the input node, and a secondary input switch for selectively coupling the input node to the shared node, wherein the secondary input switch comprises one or more transistor switches. The parasitic drain and source diodes of one or more transistor switches in secondary input switch in a selected input circuit are coupled to a voltage that is distinct from an input signal of the selected input circuit. For input circuits not selected, the parasitic drain and source diodes of secondary input switch transistor switches are coupled to an output of the amplifier.
1. A circuit, comprising:
a shared node;
a plurality of input circuits, each input circuit comprising:
an input node;
a primary input switch for selectively coupling an input to said input node; and
a secondary input switch for selectively coupling said input node to said shared node, wherein said secondary input switch comprises one or more transistor switches;
a control input for selecting one of said plurality of input circuits; and
an amplifier coupled to said shared node,
wherein parasitic drain and source diodes of each transistor switch of said secondary input switch of a selected input circuit are coupled to a voltage that is distinct from an input signal of said selected input circuit, and
wherein said parasitic drain and source diodes of each transistor switch of a secondary input switch of each input circuit that is not selected are coupled to an output of said amplifier.
2. The circuit as recited in claim 1 , wherein said circuit includes a multiplexer function.
3. The circuit as recited in claim 1 , wherein each input circuit further comprises an output switch, wherein each output switch of each corresponding input circuit couples a corresponding input node to said output of said amplifier when said corresponding input circuit is not selected and wherein a voltage drop across each secondary input switch of each input circuit that is not selected is substantially limited to an offset voltage of said amplifier.
4. The circuit as recited in claim 1 , wherein at least one of said one or more transistor switches of at least one input circuit comprises an NMOS switch and wherein said distinct voltage is a voltage that is more negative than said input signal of said selected input circuit.
5. The circuit as recited in claim 1 , wherein at least one of said one or more transistor switches of at least one input circuit comprises a PMOS switch and wherein said distinct voltage is a voltage that is more positive than said input signal of said selected input circuit.
6. The circuit as recited in claim 1 , wherein at least one of said one or more transistor switches of at least one input circuit is selected from the group consisting of junction, gallium arsenide or indium phosphide field-effect transistors.
7. The circuit as recited in claim 1 , wherein selecting one of said plurality of input circuits comprises selecting at least one of said plurality of input circuits.
8. The circuit as recited in claim 1 , wherein the circuit is fabricated as an integrated circuit.
9. A method for reducing leakage in a circuit, said method comprising the steps of:
configuring a primary input switch of at least one corresponding input circuit to selectively couple an input of said corresponding input circuit to an input node of said corresponding input circuit based on a control signal;
configuring each secondary input switch of each corresponding input circuit to selectively couple said input node of said corresponding input circuit to a shared node based on said control signal;
coupling parasitic drain and source diodes of a transistor switch of a secondary input switch of a selected input circuit to a voltage that is distinct from an input signal of said selected input circuit; and
substantially limiting leakage current of parasitic drain and source diodes of each transistor switch of a secondary input switch of each input circuit that is not selected by coupling said parasitic drain and source diodes of each transistor switch of each input circuit that is not selected to an output of an amplifier.
10. The method of claim 9 , wherein each secondary input switch has a leakage effect represented by a resistor, and wherein a voltage drop across said resistor is limited to said offset voltage when a corresponding input circuit is not selected.
11. The method of claim 9 , further comprising the step of selectively coupling each input node of each input circuit that is not selected to said output of said amplifier.
12. The method of claim 9 , wherein said transistor switch of at least one input circuit comprises an NMOS switch and wherein said distinct voltage is a voltage that is more negative than said input signal of said selected input circuit.
13. The method of claim 9 , wherein said transistor switch of at least one input circuit comprises a PMOS switch and wherein said distinct voltage is a voltage that is more positive than said input signal of said selected input circuit.