Ferroelectric memory and its manufacturing method
To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7 . Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7 c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91 . The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7 . A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92 a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.
1. A semiconductor device comprising:
a transistor that includes a gate, a source, and a drain;
a first insulator disposed on the transistor;
a first plug disposed in a first contact hole of the first insulator, the first contact hole being disposed on the source or the drain;
a lower wiring disposed on the first plug;
a second insulator disposed on the first insulator;
a first layer disposed on the second insulator, the first layer including silicon and nitrogen;
a second plug disposed in a second contact hole of the second insulator and in a third contact hole of the first layer, the second contact hole and the third contact hole being disposed continuously on the lower wiring;
a lower electrode disposed on the second plug;
a ferroelectric layer disposed on the lower electrode;
an upper electrode disposed on the ferroelectric layer;
a second layer disposed on a side of the lower electrode, the ferroelectric layer, and the upper electrode, and on a surface of the upper electrode, the second layer including alumina;
a third insulator disposed on the second layer;
a fourth contact hole of the second layer and a fifth contact hole of the third insulator being disposed continuously on the upper electrode;
an upper wiring disposed on the third insulator and in the fourth contact hole and the fifth contact hole;
a third layer disposed above the upper wiring, the third layer including alumina, TiAlN, TiAl, or TiN;
a fourth insulator disposed on the third layer; and
a plate line disposed on the fourth insulator, the plate line being connected to the upper wiring electrically.
2. The semiconductor device according to claim 1 , further comprising:
a fifth insulator disposed between the first layer and the lower electrode.
3. The semiconductor device according to claim 1 ,
the first layer being silicone nitride.
4. The semiconductor device according to claim 1 ,
the second layer being alumina.
5. The semiconductor device according to claim 1 ,
the third layer being alumina.
6. The semiconductor device according to claim 1 ,
the third layer being TiAlN.
7. The semiconductor device according to claim 1 ,
the third layer being TiAl.
8. The semiconductor device according to claim 1 ,
the third layer being TiN.