IP Library › Granted Patent US 8,433,665
Granted Patent B2
US 8,433,665 · App. 12/831,594 · Granted Apr 30, 2013

Methods and systems for three-memristor synapse with STDP and dopamine signaling

Inventors: Yi Tang (San Diego, CA); Jeffrey A. Levin (San Diego, CA); Vladimir Aparin (San Diego, CA); Venkat Rangan (San Diego, CA)
Assignee: QUALCOMM Incorporated
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,433,665
App. No.
12/831,594
Granted
Apr 30, 2013
Kind
B2
Abstract

The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.

Claims (71)

1. A synaptic electrical circuit for connection between a pre-synaptic neuron circuit and a post-synaptic neuron circuit, comprising:

a plurality of memristors to adjust a strength of the connection, wherein

a spike of the pre-synaptic neuron circuit followed by a spike of the post-synaptic neuron circuit triggers decreasing of resistance of a first of the memristors causing the strength of connection to increase, a second of the memristors being connected to the first memristor during the strength increase and a resistance of the second memristor was changed prior to the strength increase due to the spikes, and

another spike of the post-synaptic neuron circuit followed by another spike of the pre-synaptic neuron circuit triggers increasing of resistance of the first memristor causing the strength of connection to decrease, a third of the memristors being connected to the first memristor during the strength decrease and a resistance of the third memristor was changed prior to the strength decrease due to the other spikes.

2. The electrical circuit of claim 1 , wherein:

the first memristor is serially connected with the second memristor during the strength increase due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the spikes,

the resistance of the first memristor decreases as an electrical current flows through the first and second memristors, and

a voltage drop across the serial connection of the first and second memristors is constant during the flow of electrical current and based on a voltage source.

3. The electrical circuit of claim 2 , wherein the synaptic electrical circuit shares the same voltage source with one or more other synaptic electrical circuits.

4. The electrical circuit of claim 1 , wherein:

the first memristor is serially connected with the third memristor during the strength decrease due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the other spikes,

the resistance of the first memristor increases as an electrical current flows through the first and third memristors, and

a voltage drop across the serial connection of the first and third memristors is constant during the flow of electrical current and based on a voltage source.

5. The electrical circuit of claim 1 , wherein:

the first memristor is connected in parallel with the second memristor during the strength increase, and

the parallel connection of the first and second memristors is serially connected with a source of a constant electrical current due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the spikes.

6. The electrical circuit of claim 1 , wherein:

the first memristor is connected in parallel with the third memristor during the strength decrease, and

the parallel connection of the first and third memristors is serially connected with a source of a constant electrical current due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the other spikes.

7. The electrical circuit of claim 1 , wherein the resistance of the second memristor was changed exponentially with a large time constant before the strength decrease.

8. The electrical circuit of claim 1 , wherein the resistance of the third memristor was changed exponentially with a large time constant before the strength increase.

9. The electrical circuit of claim 1 , further comprising:

a pair of diodes connected to each of the memristors for controlling a direction of an electrical current flowing through that memristor.

10. A method for controlling a synaptic connection between a pre-synaptic neuron circuit and a post-synaptic neuron circuit, comprising:

increasing a strength of the connection by decreasing resistance of a first memristor of a plurality of memristors within the synaptic connection when a spike of the pre-synaptic neuron circuit is followed by a spike of the post-synaptic neuron circuit,

wherein a second of the memristors is connected to the first memristor during the strength increase and a resistance of the second memristor was changed prior to the strength increase due to the spikes; and

decreasing the strength of the connection by increasing resistance of the first memristor when another spike of the post-synaptic neuron circuit is followed by another spike of the pre-synaptic neuron circuit,

wherein a third of the memristors is connected to the first memristor during the strength decrease and a resistance of the third memristor was changed prior to the strength decrease due to the other spikes.

11. The method of claim 10 , wherein:

the first memristor is serially connected with the second memristor during the strength increase due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the spikes,

the resistance of the first memristor decreases as an electrical current flows through the first and second memristors, and

a voltage drop across the serial connection of the first and second memristors is constant during the flow of electrical current and based on a voltage source.

12. The method of claim 11 , wherein the synaptic electrical circuit shares the same voltage source with one or more other synaptic electrical circuits.

13. The method of claim 10 , wherein:

the first memristor is serially connected with the third memristor during the strength decrease due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the other spikes,

the resistance of the first memristor increases as an electrical current flows through the first and third memristors, and

a voltage drop across the serial connection of the first and third memristors is constant during the flow of electrical current and based on a voltage source.

14. The method of claim 10 , wherein:

the first memristor is connected in parallel with the second memristor during the strength increase, and

the parallel connection of the first and second memristors is serially connected with a source of a constant electrical current due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the spikes.

15. The method of claim 10 , wherein:

the first memristor is connected in parallel with the third memristor during the strength decrease, and

the parallel connection of the first and third memristors is serially connected with a source of a constant electrical current due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the other spikes.

16. The method of claim 10 , wherein the resistance of the second memristor was changed exponentially with a large time constant before the strength decrease.

17. The method of claim 10 , wherein the resistance of the third memristor was changed exponentially with a large time constant before the strength increase.

18. The method of claim 10 , further comprising:

connecting a pair of diodes to each of the memristors to control a direction of an electrical current flowing through that memristor.

19. An apparatus for controlling a synaptic connection between a pre-synaptic neuron circuit and a post-synaptic neuron circuit, comprising:

means for increasing a strength of the connection by decreasing resistance of a first memristor of a plurality of memristors within the synaptic connection when a spike of the pre-synaptic neuron circuit is followed by a spike of the post-synaptic neuron circuit,

wherein a second of the memristors is connected to the first memristor during the strength increase and a resistance of the second memristor was changed prior to the strength increase due to the spikes; and

means for decreasing the strength of the connection by increasing resistance of the first memristor when another spike of the post-synaptic neuron circuit is followed by another spike of the pre-synaptic neuron circuit,

wherein a third of the memristors is connected to the first memristor during the strength decrease and a resistance of the third memristor was changed prior to the strength decrease due to the other spikes.

20. The apparatus of claim 19 , wherein:

the first memristor is serially connected with the second memristor during the strength increase due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the spikes,

the resistance of the first memristor decreases as an electrical current flows through the first and second memristors, and

a voltage drop across the serial connection of the first and second memristors is constant during the flow of electrical current and based on a voltage source.

21. The apparatus of claim 20 , wherein the synaptic electrical circuit shares the same voltage source with one or more other synaptic electrical circuits.

22. The apparatus of claim 19 , wherein:

the first memristor is serially connected with the third memristor during the strength decrease due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the other spikes,

the resistance of the first memristor increases as an electrical current flows through the first and third memristors, and

a voltage drop across the serial connection of the first and third memristors is constant during the flow of electrical current and based on a voltage source.

23. The apparatus of claim 19 , wherein:

the first memristor is connected in parallel with the second memristor during the strength increase, and

the parallel connection of the first and second memristors is serially connected with a source of a constant electrical current due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the spikes.

24. The apparatus of claim 19 , wherein:

the first memristor is connected in parallel with the third memristor during the strength decrease, and

the parallel connection of the first and third memristors is serially connected with a source of a constant electrical current due to a pulse of a signal being input to the synaptic electrical circuit and generated based on the other spikes.

25. The apparatus of claim 19 , wherein the resistance of the second memristor was changed exponentially with a large time constant before the strength decrease.

26. The apparatus of claim 19 , wherein the resistance of the third memristor was changed exponentially with a large time constant before the strength increase.

27. The apparatus of claim 19 , further comprising:

means for connecting a pair of diodes to each of the memristors to control a direction of an electrical current flowing through that memristor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2010
From: TANG, YI; LEVIN, JEFFREY A.; RANGAN, VENKAT; APARIN, VLADIMIR
To: QUALCOMM INCORPORATED
Reel/Frame 025427/0043 →
Continuity (1)
Related Publication 20120011090A1 · Jan 12, 2012