IP Library › Granted Patent US 9,037,279
Granted Patent B2
US 9,037,279 · App. 12/831,597 · Granted May 19, 2015

Clustering for prediction models in process control and for optimal dispatching

Inventors: Francis Ko (Taichung, TW); Tzu-yu Wang (Taipei, TW); Kewei Zuo (Yonghe, TW); Henry Lo (Hsin-Chu, TW); Jean Wang (Hsin-Chu, TW); Chih-Wei Lai (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
G05B17/02
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Quick Facts
Patent No.
US 9,037,279
App. No.
12/831,597
Granted
May 19, 2015
Kind
B2
Abstract

A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

Claims (35)

1. A method for semiconductor process control, the method comprising:

using at least one processor:

clustering processing tools of a processing stage into a tool cluster based on processing data; and

forming a prediction model of a physical characteristic of a semiconductor wafer based on the tool cluster.

2. The method of claim 1 , wherein the clustering includes using a k-mean algorithm.

3. The method of claim 2 , wherein a fixed number of centroids are introduced into an n-dimensional space, wherein the n-dimensional space contains data-points representative of the processing tools and n is a number of parameters represented.

4. The method of claim 2 , wherein a variable number of centroids are introduced into an n-dimensional space, wherein the n-dimensional space contains data-points representative of the processing tools and n is a number of parameters represented.

5. The method of claim 2 , wherein the prediction model is based on a centroid of the tool cluster.

6. The method of claim 1 , wherein the clustering includes using an analysis of variance (ANOVA).

7. The method of claim 6 , wherein the tool cluster comprises the processing tools that have tool identifications (IDs), inline data, or wafer acceptance test (WAT) results that result in a p-value of less than 0.05 from the ANOVA.

8. The method of claim 1 , wherein the clustering includes using a c-clustering algorithm or a top-down or bottom-up tree methodology.

9. The method of claim 1 , wherein the clustering the processing tools of the processing stage into the tool cluster comprises clustering first processing stage tools of a first processing stage into first stage tool clusters, and clustering second processing stage tools of a second processing stage into second stage tool clusters.

10. The method of claim 9 further comprising:

identifying cluster routes between each first stage tool cluster and each second stage tool cluster; and

ranking each cluster route such that a rank assigned to each cluster route identifies an ability of each cluster route to optimize wafer processing uniformity comparatively with the other cluster routes.

11. The method of claim 10 further comprising scheduling processing of wafers, wherein some of the wafers that require high uniformity are processed on one of the cluster routes with a high rank representing a comparatively high optimization of wafer processing uniformity, and wherein others of the wafers that do not require high uniformity are processed on another of the cluster routes.

12. A method for semiconductor process control, the method comprising:

providing cluster routes between first stage tool clusters and second stage tool clusters, wherein each cluster route is between one first stage tool cluster and one second stage tool cluster; and

using at least one processor:

assigning a comparative optimization ranking to each cluster route, wherein the comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity, and

scheduling processing of wafers, wherein wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wherein wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

13. The method of claim 12 further comprising:

dispatching the wafers that require high wafer processing uniformity along the one cluster route that has a high comparative optimization ranking; and

dispatching the wafers that do not require high wafer processing uniformity along the other cluster route.

14. The method of claim 12 , wherein the providing the cluster routes between the first stage tool clusters and the second stage tool clusters comprises clustering first stage processing tools into the first stage tool clusters, and clustering second stage processing tools into the second stage tool clusters.

15. The method of claim 14 , wherein the clustering the first stage processing tools and the clustering the second stage processing tools each includes using a k-mean algorithm, an analysis of variance (ANOVA), a c-clustering algorithm, or a top-down or bottom-up tree methodology.

16. The method of claim 14 , wherein the clustering the first stage processing tools and the clustering the second stage processing tools each includes clustering based on processing data.

17. A system for semiconductor wafer processing, the system comprising:

first stage processing tools;

second stage processing tools;

a clustering tool to cluster the first stage processing tools into first stage tool clusters and to cluster the second stage processing tools into second stage tool clusters; and

a scheduling tool to schedule wafer processing along cluster routes between the first stage tool clusters and the second stage tool clusters and based on a comparative ranking of the cluster routes, the comparative ranking being based on a characteristic of wafers processed by the respective cluster routes, wherein each cluster route is between one first stage tool cluster and one second stage tool cluster.

18. The system of claim 17 , wherein the cluster routes are ranked comparatively based on wafer processing uniformity, and wherein the scheduling tool schedules a first group of wafers that requires high processing uniformity to be processed along one cluster route that has a ranking indicating a highest wafer processing uniformity.

19. The system of claim 17 , wherein the clustering tool clusters the first stage tool clusters and the second stage tool clusters based on processing data using a k-mean algorithm, an analysis of variance (ANOVA), a c-clustering algorithm, or a top-down or bottom-up tree methodology.

20. The system of claim 19 , wherein processing data includes chamber parameter data, tool identifications (IDs), inline data, or wafer acceptance test (WAT) results.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2015
From: KO, FRANCIS; WANG, TZU-YU; ZUO, KEWEI; LO, HENRY; WANG, JEAN; LAI, CHIH-WEI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 035412/0056 →
Continuity (2)
Provisional Application 61240743 · Sep 9, 2009
Related Publication 20110060441A1 · Mar 10, 2011