IP Library Granted Patent US 8,471,365
Granted Patent B2
US 8,471,365 · App. 12/833,145 · Granted Jun 25, 2013

Nitride semiconductor substrate, semiconductor device, and methods for manufacturing nitride semiconductor substrate and semiconductor device

Inventors: Sayuri Yamaguchi (Itami, JP); Naoki Matsumoto (Itami, JP); Hidenori Mikami (Itami, JP)
Assignee: Sumitomo Electric Industries, Ltd.
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Quick Facts
Patent No.
US 8,471,365
App. No.
12/833,145
Granted
Jun 25, 2013
Kind
B2
Abstract

A nitride semiconductor substrate having a main surface serving as a semipolar plane and provided with a chamfered portion capable of effectively preventing cracking and chipping, a semiconductor device fabricated using the nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate and the semiconductor device are provided. The nitride semiconductor substrate includes a main surface inclined at an angle of 71° or more and 79° or less with respect to the (0001) plane toward the [1-100] direction or inclined at an angle of 71° or more and 79° or less with respect to the (000-1) plane toward the [−1100] direction; and a chamfered portion located at an edge of an outer periphery of the main surface. The chamfered portion is inclined at an angle θ 1 or θ 2 of 5° or more and 45° or less with respect to adjacent one of the main surface and a backside surface on a side opposite to the main surface. Accordingly, cracking and chipping occurring from the edge of the outer periphery of the nitride semiconductor substrate can be effectively suppressed.

Claims (10)

1. A nitride semiconductor substrate comprising:

a main surface inclined at an angle of 71° or more and 79° or less with respect to a (0001) plane toward a [1-100] direction or inclined at an angle of 71° or more and 79° or less with respect to a (000-1) plane toward a [−1100] direction; and

a chamfered portion located at an edge of an outer periphery of said main surface,

said chamfered portion being inclined at an angle of 5° or more and 45° or less with respect to adjacent one of said main surface and a backside surface on a side opposite to said main surface,

said chamfered portion includes a topside chamfer formed on the main surface side and a backside chamfer formed on the backside surface side, and

a damaged layer formed in the topside chamfer has a thickness greater than that of a damaged layer formed in the backside chamfer.

2. The nitride semiconductor substrate according to claim 1 , wherein a damaged layer having an average thickness of 0.5 μm or more and 10 μm or less is formed on a surface layer of said chamfered portion.

3. The nitride semiconductor substrate according to claim 1 , wherein a chamfering amount of said chamfered portion is 0.02 mm or more and 0.5 mm or less.

4. The nitride semiconductor substrate according to claim 1 , wherein a surface roughness of said chamfered portion is 0.07 μm or more and 3 μm or less in terms of Ra.

5. A semiconductor device fabricated using the nitride semiconductor substrate according to claim 1 .

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Dec 7, 2023
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUBISHI CHEMICAL CORPORATION
Reel/Frame 065817/0967 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2010
From: YAMAGUCHI, SAYURI; MATSUMOTO, NAOKI; MIKAMI, HIDENORI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 024658/0706 →
Priority Claims (1)
JP 2009-218890 · Sep 24, 2009 · national
Continuity (1)
Related Publication 20110068434A1 · Mar 24, 2011