Interrupt generation and acknowledgment for RFID

1. A circuit controlling memory access comprising:

a memory;

a memory access control circuit coupled to the memory;

an RFID interface coupled to the memory access control circuit;

a secondary interface coupled to the memory access control circuit; and

an interrupt manager coupled to the memory access control circuit, the RFID interface, and the secondary interface, wherein the RFID interface allows the secondary interface to have access to the memory, the interrupt manager is configured to receive an interrupt command through the RFID interface, and the secondary interface is configured to acknowledge the interrupt command.

2. The circuit of claim 1 wherein the interrupt manager is configured to release the secondary interface for subsequent accesses.

3. The circuit of claim 1 wherein the interrupt manager is configured to disable the RFID interface from accessing the memory.

4. The circuit of claim 1 wherein the interrupt manager is configured to receive a termination command through the secondary interface.

5. The circuit of claim 4 wherein the interrupt manager is configured to disable the secondary interface.

6. The circuit of claim 4 wherein the interrupt manager is configured to enable the RFID interface.

7. The circuit of claim 1 wherein the memory comprises a FRAM memory.

8. The circuit of claim 1 wherein only one of the RFID interface or secondary interface is configured to be operational at a time.

9. An interrupt method for an RFID circuit having an RFID interface and a secondary interface, the interrupt method comprising:

receiving an interrupt signal through the RFID interface;

sending the interrupt signal to the secondary interface;

disabling the RFID interface;

receiving an interrupt end signal by the secondary interface;

clearing the interrupt signal; and

enabling the RFID interface.

10. The method of claim 9 further comprising generating the interrupt signal using first and second trigger addresses.

11. The method of claim 10 further comprising generating the interrupt signal by XORing first and second trigger data.

12. The method of claim 9 further comprising using the RFID interface and the secondary interface to alternatively write data to a memory.

13. The method of claim 11 wherein the memory comprises a FRAM memory.

14. The method of claim 9 wherein the secondary interface communicates with an embedded microprocessor that generates the interrupt end signal.

15. A circuit controlling memory access comprising:

a memory;

a memory access control circuit coupled to the memory;

an RFID interface coupled to the memory access control circuit;

a secondary interface coupled to the memory access control circuit; and

an interrupt manager coupled to the memory access control circuit, the RFID interface, and the secondary interface, wherein the RFID interface allows the secondary interface to have access to the memory, the interrupt manager is configured to receive an interrupt command through the RFID interface, and the interrupt manager is configured to receive a termination command through the secondary interface.

16. The circuit of claim 15 wherein the secondary interface is configured to acknowledge the interrupt command.

17. The circuit of claim 16 wherein the interrupt manager is configured to release the secondary interface for subsequent accesses.

18. The circuit of claim 16 wherein the interrupt manager is configured to disable the RFID interface from accessing the memory.

19. The circuit of claim 15 wherein the interrupt manager is configured to disable the secondary interface.

20. The circuit of claim 15 wherein the interrupt manager is configured to enable the RFID interface.

21. The circuit of claim 15 wherein the memory comprises a FRAM memory.

22. The circuit of claim 15 configured to operate only one of the RFID interface or secondary interface at a time.