Three-dimensional phase-change memory array
View Patent ↗A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements disposed above the first and second plurality of diodes and a second plurality of memory elements disposed above the first plurality of memory elements.
1. A memory array, comprising:
a substrate;
a plurality of first lower conductive lines disposed on said substrate;
a plurality of first upper conductive lines disposed above said first lower conductive lines;
a plurality of second lower conductive lines disposed above said first lower conductive lines and disposed below said first upper conductive lines;
a plurality of second upper conductive lines disposed above said second lower conductive lines;
a plurality of first phase-change memory cells, each of said first phase-change memory cells coupled between one of said first lower conductive lines and one of said first upper conductive lines; and
a plurality of second phase-change memory cells, each of said second phase-change memory cells coupled between one of said second lower conductive lines and one of said second upper conductive lines.
2. The memory array of claim 1 , wherein said first lower conductive lines and said first upper conductive lines are parallel.
3. The memory array of claim 1 , wherein said first lower conductive lines and said second lower conductive lines cross.
4. The memory array of claim 1 , wherein said first phase-change memory cells are electrically isolated from said second phase-change memory cells.
5. The memory array of claim 1 , wherein each of said first phase-change memory cells includes a first phase-change memory element in series with a first isolation element and each of said second phase-change memory cells includes a second phase-change memory element in series with a second isolation element.
6. The memory array of claim 5 , wherein said second isolation elements are disposed above said first isolation elements.
7. The memory array of claim 5 , wherein said first phase-change memory elements are disposed above said second isolation elements.
8. The memory array of claim 5 , wherein said second phase-change memory elements are disposed above said first phase-change memory elements.
9. The memory array of claim 5 , where each of said isolation elements are diodes.
10. The memory array of claim 5 , wherein a first conductive plug interconnects each of said first isolation elements with one of said first phase-change memory elements.
11. The memory array of claim 10 , wherein a second conductive plug interconnects each of said second isolation elements with one of said second phase-change memory elements.
12. The memory array of claim 11 , wherein said first conductive plug is electrically isolated from said second conductive plug.
13. The memory array of claim 1 , wherein each of said phase-change memory cells includes a chalcogenide material.
14. The memory array of claim 1 , wherein the projection of said first lower conductive lines onto said substrate overlaps the projection of said second lower conductive lines onto said substrate.
15. The memory array of claim 14 , wherein the projection of said first upper conductive lines onto said substrate overlaps the projection of said second upper conductive lines onto said substrate.
16. The memory array of claim 1 , wherein the projection of said first phase-change memory cells onto said substrate overlaps the projection of said second phase-change memory cells onto said substrate.
17. The memory array of claim 1 , wherein said second upper conductive lines are disposed above said first upper conductive lines.