Automatic optimal integrated circuit generator from algorithms and specification

1. A method to automatically design a custom integrated circuit, comprising:

a. receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit;

b. automatically devising an application specific instruction set (ASIS) processor architecture custom tailored to the computer readable code and generating a processor chip specification with a compiler generated for each ASIS processor architecture, said generated processor chip specification is uniquely customized to the computer readable code which satisfies the constraints; and

c. synthesizing using a computer the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.

2. The method of claim 1 , comprising performing static profiling or dynamic profiling of the computer readable code.

3. The method of claim 1 , further comprising automatically generating firmware or software development kit (SDK) for the custom integrated circuit to run the computer readable code.

4. The method of claim 1 , further comprising selecting an architecture based on the computer readable code.

5. The method of claim 1 , further comprising optimizing the architecture based on static and dynamic profiling of the computer readable code.

6. The method of claim 1 , further comprising compiling the computer readable code into assembly code in a programmable architecture.

7. The method of claim 6 , further comprising linking the assembly code to generate firmware for the selected programmable architecture.

8. The method of claim 7 , further comprising performing cycle accurate simulation of the firmware.

9. The method of claim 7 , further comprising performing dynamic profiling of the firmware.

10. The method of claim 9 , further comprising optimizing the programmable architecture based on profiled firmware.

11. The method of claim 7 , further comprising optimizing the programmable architecture based on the assembly code.

12. The method of claim 1 , further comprising generating register transfer level (RTL) code for the selected architecture.

13. The method of claim 12 , further comprising performing synthesis of the RTL code.

14. A system to automatically design a custom integrated circuit, comprising:

a. means for receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit;

b. means for automatically devising an application specific instruction set (ASIS) processor architecture custom tailored to the computer readable code and generating a processor chip specification with a compiler generated for each ASIS processor architecture, said generated processor chip specification is uniquely customized to the computer readable code which satisfies the constraints; and

c. means for synthesizing using a computer the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

15. The system of claim 14 , further comprising means for performing static and dynamic profiling of the computer readable code.

16. The system of claim 14 , further comprising means for selecting an architecture based on the computer readable code.

17. The system of claim 14 , further comprising means for optimizing the architecture based on profiles of the computer readable code.

18. The system of claim 14 , further comprising a compiler to convert the computer readable code into assembly code.

19. The system of claim 14 , further comprising a cycle accurate simulator to test the firmware.

20. The system of claim 14 , further comprising a register transfer level code generator for the selected architecture.