Application driven power gating
Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
1. A method to manage power in a custom integrated circuit (IC) design, comprising:
a. receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage;
b. automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop (CIL) to compile, assemble and link code for each processor architecture iteration, the processor architecture generated by the CIL having one or more processing blocks and one or more power domains;
c. generating functional block usage statistics from the profile and tracking usage of different processing blocks as a function of time;
d. determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and
e. gating the power domains with power based on the code profile; and
f. identifying from the generated iterations the optimal architecture and synthesizing the optimal architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
2. The method of claim 1 , comprising speculatively shutting down power for one or more processing blocks and automatically switching power on for turned off processing blocks when needed.
3. The method of claim 1 , comprising using an instruction decoder to determine when power is to be applied to each power domain.
4. The method of claim 1 , comprising performing static profiling or dynamic profiling of the computer readable code to determine processing block usage.
5. The method of claim 1 , comprising automatically generating firmware or software development kit (SDK) for the custom integrated circuit to run the computer readable code.
6. The method of claim 1 , comprising compiling the computer readable code into assembly code.
7. The method of claim 6 , comprising linking the assembly code to generate firmware for the selected architecture.
8. The method of claim 6 , comprising performing cycle-based simulation of the firmware.
9. The method of claim 6 , comprising performing dynamic profiling of the firmware.
10. The method of claim 9 , comprising optimizing the architecture based on profiled firmware.
11. The method of claim 6 , comprising optimizing the architecture based on the assembly code.
12. The method of claim 1 , comprising generating register transfer level code for the selected architecture.
13. The method of claim 9 , comprising performing synthesis of the RTL code.
14. A system having a processor to automatically manage power in a custom integrated circuit (IC) design, comprising:
a. means for receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage;
b. means for automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture generated by the CIL having one or more processing blocks and one or more power domains;
c. means for generating functional block usage statistics from the profile and tracking usage of different processing blocks as a function of time;
d. means for determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and
e. means for gating the power domains with power based on the code profile; and
f. means for identifying from the generated iterations the optimal architecture and synthesizing the optimal architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
15. The system of claim 14 , comprising means for speculatively shutting down power for one or more processing blocks and automatically switching power on for turned off processing blocks when needed.
16. The system of claim 14 , comprising an instruction decoder to determine when power is to be applied to each power domain.