IP Library Granted Patent US 8,729,550
Granted Patent B2
US 8,729,550 · App. 12/835,906 · Granted May 20, 2014

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Junichiro Sakata (Atsugi, JP); Hiroyuki Miyake (Atsugi, JP); Hideaki Kuwabara (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,729,550
App. No.
12/835,906
Granted
May 20, 2014
Kind
B2
Abstract

An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.

Claims (95)

1. A semiconductor device comprising:

a pixel portion including a first transistor and a pixel electrode over a substrate; and

a driver circuit including a second transistor over the substrate,

wherein the first transistor comprises:

a first gate electrode over the substrate;

a gate insulating layer over the first gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

a first channel protective layer over and in contact with a part of the first oxide semiconductor layer; and

a first source electrode and a first drain electrode over the first channel protective layer and the first oxide semiconductor layer,

wherein the second transistor comprises:

a second gate electrode over the substrate;

the gate insulating layer over the second gate electrode;

a second oxide semiconductor layer over the gate insulating layer;

a second channel protective layer over and in contact with a part of the second oxide semiconductor layer;

a second source electrode and a second drain electrode over the second channel protective layer and the second oxide semiconductor layer; and

a third gate electrode over the second channel protective layer,

wherein the third gate electrode overlaps with the second gate electrode,

wherein the pixel electrode is electrically connected to one of the first source electrode and the first drain electrode, and

wherein the third gate electrode and the pixel electrode are provided on a same surface.

2. The semiconductor device according to claim 1 , wherein the first channel protective layer and the second channel protective layer comprise the same insulating material which has a light-transmitting property.

3. The semiconductor device according to claim 1 , wherein the second source electrode and the second drain electrode are a film formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a stacked film including the film and an alloy film thereof.

4. The semiconductor device according to claim 1 , wherein the first source electrode, the first drain electrode, and the pixel electrode comprise any of indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, and zinc oxide.

5. The semiconductor device according to claim 1 , further comprises a capacitor portion over the substrate,

wherein the capacitor portion comprises:

a capacitor wiring; and

a capacitor electrode overlapping with the capacitor wiring, and

wherein the capacitor wiring and the capacitor electrode have a light-transmitting property.

6. The semiconductor device according to claim 1 ,

wherein the first channel protective layer and the second channel protective layer comprise an oxide insulating film.

7. The semiconductor device according to claim 1 ,

wherein a first portion of the first oxide semiconductor layer is in contact with the first channel protective layer,

wherein a second portion of the first oxide semiconductor layer is not in contact with the first channel protective layer, and

wherein a carrier concentration of the second portion is larger than a carrier concentration of the first portion.

8. The semiconductor device according to claim 1 ,

wherein a first portion of the first oxide semiconductor layer is in contact with the first channel protective layer,

wherein a second portion of the first oxide semiconductor layer is not in contact with the first channel protective layer, and

wherein a carrier concentration of the first portion is less than 1×10 17 /cm 3 , and

wherein a carrier concentration of the second portion is equal to or more than 1×10 17 /cm 3 .

9. The semiconductor device according to claim 1 , further comprising:

a first protective insulating layer over and in contact with the first channel protective layer and the second channel protective layer; and

a second protective insulating layer over the first protective insulating layer,

wherein the third gate electrode is formed over and in contact with the first protective insulating layer.

10. The semiconductor device according to claim 1 , further comprising:

a first protective insulating layer over and in contact with the first channel protective layer and the second channel protective layer; and

a second protective insulating layer over the first protective insulating layer,

wherein the third gate electrode is formed over and in contact with the second protective insulating layer.

11. A semiconductor device comprising:

a pixel portion including a first transistor and a pixel electrode over a substrate; and

a driver circuit including a second transistor over the substrate,

wherein the first transistor comprises:

a first gate electrode over the substrate;

a gate insulating layer over the first gate electrode;

a first oxide semiconductor layer over the gate insulating layer;

a first channel protective layer over and in contact with a part of the first oxide semiconductor layer; and

a first source electrode and a first drain electrode over the first channel protective layer and the first oxide semiconductor layer,

wherein the second transistor comprises:

a second gate electrode over the substrate;

the gate insulating layer over the second gate electrode;

a second oxide semiconductor layer over the gate insulating layer;

a second channel protective layer over and in contact with a part of the second oxide semiconductor layer;

a second source electrode and a second drain electrode over the second channel protective layer and the second oxide semiconductor layer; and

a third gate electrode over the second channel protective layer,

wherein the third gate electrode overlaps with the second gate electrode,

wherein the pixel electrode is electrically connected to one of the first source electrode and the first drain electrode,

wherein the first gate electrode, the gate insulating layer, the first oxide semiconductor layer, the first source electrode, the first drain electrode, the first channel protective layer, and the pixel electrode have a light-transmitting property,

wherein each of the first source electrode and the first drain electrode comprises an oxide conductive material,

wherein each of the second source electrode and the second drain electrode comprises a metal, and

wherein the third gate electrode and the pixel electrode are provided on a same surface.

12. The semiconductor device according to claim 11 , wherein the first channel protective layer and the second channel protective layer comprise the same insulating material which has a light-transmitting property.

13. The semiconductor device according to claim 11 , wherein the metal is one selected from Al, Cr, Cu, Ta, Ti, Mo, and W.

14. The semiconductor device according to claim 11 , wherein the oxide conductive material comprises any of indium oxide, an alloy of indium oxide and tin oxide, an alloy of indium oxide and zinc oxide, and zinc oxide.

15. The semiconductor device according to claim 11 , further comprises a capacitor portion over the substrate,

wherein the capacitor portion comprises:

a capacitor wiring; and

a capacitor electrode overlapping with the capacitor wiring, and

wherein the capacitor wiring and the capacitor electrode have a light-transmitting property.

16. The semiconductor device according to claim 11 ,

wherein the first channel protective layer and the second channel protective layer comprise an oxide insulating film.

17. The semiconductor device according to claim 11 ,

wherein a first portion of the first oxide semiconductor layer is in contact with the first channel protective layer,

wherein a second portion of the first oxide semiconductor layer is not in contact with the first channel protective layer, and

wherein a carrier concentration of the second portion is larger than a carrier concentration of the first portion.

18. The semiconductor device according to claim 11 ,

wherein a first portion of the first oxide semiconductor layer is in contact with the first channel protective layer,

wherein a second portion of the first oxide semiconductor layer is not in contact with the first channel protective layer, and

wherein a carrier concentration of the first portion is less than 1×10 17 /cm 3 , and

wherein a carrier concentration of the second portion is equal to or more than 1×10 17 /cm 3 .

19. The semiconductor device according to claim 11 , further comprising:

a first protective insulating layer over and in contact with the first channel protective layer and the second channel protective layer; and

a second protective insulating layer over the first protective insulating layer,

wherein the third gate electrode is formed over and in contact with the first protective insulating layer.

20. The semiconductor device according to claim 11 , further comprising:

a first protective insulating layer over and in contact with the first channel protective layer and the second channel protective layer; and

a second protective insulating layer over the first protective insulating layer,

wherein the third gate electrode is formed over and in contact with the second protective insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2010
From: YAMAZAKI, SHUNPEI; SAKATA, JUNICHIRO; MIYAKE, HIROYUKI; KUWABARA, HIDEAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 024682/0021 →
Priority Claims (1)
JP 2009-169601 · Jul 18, 2009 · national
Continuity (1)
Related Publication 20110012117A1 · Jan 20, 2011